CONV_INTEGER problems

Discussion in 'VHDL' started by Giox, Feb 12, 2006.

  1. Giox

    Giox Guest

    Hello everybody, I have the followin code:

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all

    ......SNIP.....
    signal high_registered : std_logic_vector(1 downto 0);
    signal high_current : std_logic_vector(1 downto 0);

    ......SNIP.....

    busy_condition <= '1' WHEN CONV_INTEGER(high_registered) >
    CONV_INTEGER(high_current)
    ELSE '0';
    ......SNIP.....

    During simulation:
    high_registered "10";
    high_current "00";

    The resulting busy_condition is Z.... what's wrong?
    Any help will be appreciated
    Gio
     
    Giox, Feb 12, 2006
    #1
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  2. Giox

    Arnaud Guest

    I suggest that you simply used a conversion to unsigned instead of the
    non standard function conv_integer:

    busy_condition <= '1' WHEN unsigned(high_registered) >
    unsigned(high_current)
    ELSE '0';

    I also suggest that you used library ieee.numeric_std.all; instead of
    ieee.std_logic_arith.all;

    Regards,

    Arnaud
     
    Arnaud, Feb 12, 2006
    #2
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  3. Giox

    anupam Guest

    hi,
    The library arith has both signed and unsigned defined in it so while
    converting to interger ,you need to specify that your std_logic is
    signed or unsigned ....

    Just include "use ieee.std_logic_unsigned.all" or "use
    ieee.std_signed.all" to make it happen

    regards,
    Anupam Jain
     
    anupam, Feb 13, 2006
    #3
  4. Giox

    Giox Guest

    Thanks a lot now it works !
     
    Giox, Feb 13, 2006
    #4
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