conversion variable to std_logic

[Dr. Thomas Ansorg]

Hello all
I need to convert a variable to a std_logic or std_logic_vector for
monitoring in the simulation. The variable is a natural range 0 to 39.

Tom

 

[Andy]

Hello all
I need to convert a variable to a std_logic or std_logic_vector for
monitoring in the simulation. The variable is a natural range 0 to 39.

Tom

use ieee.numeric_std.all;

....

sig <= std_logic_vector(to_unsigned(var, sig'length));

However, signals can be integer/natural types too, or
numeric_std.signed/unsigned. On device level ports, post-synthesis/P&R
gate level netlists will use SL/SLV datatypes on those ports no matter
what your RTL used (or you can build a type conversion wrapper for the
device when/if the gate level netlist is needed for simulation). For
internal signals & ports, use whatever makes the most sense.

Andy