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Hello, I'm new in VHDL.
I have a basic question, but 3 hours of searches didn't provide any useful answer.
I got two SIGNALs, one unsigned, the other signed. I want to do something like :
How should I do ?
I have a basic question, but 3 hours of searches didn't provide any useful answer.
I got two SIGNALs, one unsigned, the other signed. I want to do something like :
Code:
SIGNAL Consigne_TMP : signed(7 DOWNTO 0);
SIGNAL Mot_Labview : unsigned(7 DOWNTO 0);
Mot_Labview(7) <= to_unsigned(Consigne_TMP(7), 8);
How should I do ?