Convert Between Enumeration and Integer Values

[Olaf Petzold]

Hi,

I've read the FAQ 4.2.21 "How to Convert Between Enumeration and
Integer Values". Anyway, I have questions to these function:

function slv2pec (
signal id : std_logic_vector(2 downto 0))
-- signal id : std_logic_vector(natural range <>))
return pattern_edge_comb_t is

begin
-- Error: No feasible entries for infix operator "<".
-- assert (pattern_edge_comb_t'high < 4) -- Line 89
-- report "Conversation error (wrong assumptions)." severity
error;
return pattern_edge_comb_t'val(to_integer(unsigned(id))); --L91
end function slv2pec;


with:

type pattern_edge_comb_t is (
unknown,
and_comb,
or_comb,
xor_comb);

I would like write the signal is unconstrained, but I get a syntax
error on this. Would be very usefull.

Furthermore the assert is recommanded by me ;-)

** Error: (89): No feasible entries for infix operator "<".
** Error: (89): Type error resolving infix expression "<".

Last, I get the synthesis error:
line 91: Attribute is not authorized : 'val'.

How can I resolve this problems?

Thanks and Regards,
Olaf

 

[Mike Treseler]

I've read the FAQ 4.2.21 "How to Convert Between Enumeration and Integer ....
type pattern_edge_comb_t is (
unknown,
and_comb,
or_comb,
xor_comb);

process (clk) is
subtype pat_t is pattern_edge_comb_t'range
variable n_v : pat_t;
begin
n_v := pat_t'pos(or_comb);
...

-- Mike Treseler

 

[Olaf Petzold]

process (clk) is
subtype pat_t is pattern_edge_comb_t'range
variable n_v : pat_t;
begin
n_v := pat_t'pos(or_comb);
...

thank you, unfortunally it doesn't work:

subtype pat_t is pattern_edge_comb_t'range;

** Error: Attribute "range" requires an array prefix.
** Error: Expecting a type name, found attribute name "range" instead.

even if it clear wath's the purpose is (variable idx : natural range
slv'low to slv'high works).

Regards,
Olaf

 

[Olaf Petzold]

anyway, it seems to me, that the xilinx tools the attribute pos and
val doesn't support. Can someone confirm this? I'm using xst 7.1.04.

Regards,
Olaf

 

[Mike Treseler]

thank you, unfortunally it doesn't work:

You're right.
See function enum2nat below.

-- Mike Treseler

------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity enum_nat is
end enum_nat;

architecture sim of enum_nat is
begin
process is
type pattern_edge_comb_t is (
unknown, and_comb, or_comb, xor_comb
);
variable n_v : natural;
function enum2nat (enum_arg : pattern_edge_comb_t)
return integer is
begin
return pattern_edge_comb_t'pos(enum_arg);
end function enum2nat;
begin
for t in pattern_edge_comb_t loop
n_v := enum2nat(t);
report integer'image(n_v) & " is "
& pattern_edge_comb_t'image(t);
end loop;
wait;
end process;
end architecture sim;
------------------------------
--# vsim -c enum_nat
--# Loading work.enum_nat(sim)
--VSIM 1> run
--# ** Note: 0 is unknown
--# ** Note: 1 is and_comb
--# ** Note: 2 is or_comb
--# ** Note: 3 is xor_comb