Convert from std_logic_vector to real

Discussion in 'VHDL' started by eNo, Aug 4, 2005.

  1. eNo

    eNo Guest

    Is there a standard library function (e.g., to_real) to convert a
    std_logic_vector to a real value? If not, how would one go about doing this?
     
    eNo, Aug 4, 2005
    #1
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  2. eNo wrote:

    > Is there a standard library function (e.g., to_real) to convert a
    > std_logic_vector to a real value? If not, how would one go about doing this?


    With IEEE.numeric_std.all

    signal slv : std_logic_vector(bitwidth-1 downto 0);
    signal sru,srs : real;

    sru<=to_real(to_integer(unsigned(slv)));
    -- or
    srs<=to_real(to_integer(signed(slv)));


    It looks not nice with IEEE.numeric_std, but as noted the decision for
    signed / unsigned is nessecary and therefore IEEE.numeric_std is
    recommended.

    Ralf
     
    Ralf Hildebrandt, Aug 5, 2005
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  3. eNo

    Hubble Guest

    The problem lies in the fact that you can represent real values in
    different ways as bits. The IEEE floating point format defines a
    standard doing this for single/double precision. First converting to a
    signed or unsigned integer does not solve the problem in all cases. I
    do not know of any standard library functions to convert
    std_logic_vector representations of IEEE floating point to real.

    As the term "floating point" suggests, the decimal point floats. An
    part of the format (exponent) defines the position of the decimal point
    here.

    In hardware, often fixed point arithmetic will do. You could use 24
    bits before and 8 bits after the decimal point. In this case, convert
    to integer, divide by 2**8 and assign to the real value.

    Integer aithmetic in VHDL is restricted to the range integer'low to
    integer'high, which is only guaranteed to work for vectors up to 32
    bits, so first converting to integer and then to real may not work for
    larger vectors

    Hubble.
     
    Hubble, Aug 9, 2005
    #3
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