convert Verilog code to vhdl (simple program) help me please

[imaginary]

Hello..

I need to convert this Verilog code to VHDL , help me please..

the program find the third power of x
ex: if x=2 then the third power of x is 8

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module power3(
output [7:0] XPower,
output finished,
input [7:0] X,
input clk, start); // the duration of start is a
single clock
reg [7:0] ncount;
reg [7:0] XPower;
assign finished = (ncount == 0);
always@(posedge clk)
if(start) begin
XPower <= X;
ncount <= 2;
end
else if(!finished) begin
ncount <= ncount - 1;
XPower <= XPower * X;
end
endmodule
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