Converting synthesized VHDL/Verilog to spice netlist

Discussion in 'VHDL' started by Noohul Ali, Apr 21, 2005.

  1. Noohul Ali

    Noohul Ali Guest

    Dear All,
    I'm trying to get Spice netlist file from Verilog/VHDL. After I
    synthesized the vhdl file using Synplify, what tools available that
    can help me to get the spice netlist. I need the interconnect
    information incorporated in the spice netlist. Any help will be very
    useful
    Thanks,
    ali
     
    Noohul Ali, Apr 21, 2005
    #1
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  2. Noohul Ali

    Neo Guest

    I think a backend layout tool would be able to do it. at least verilog
    to spice conversion is done by mentor tool.
     
    Neo, Apr 28, 2005
    #2
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  3. Noohul Ali

    Neo Guest

    I think a backend layout tool would be able to do it. at least verilog
    to spice is done by mentors tool.
     
    Neo, Apr 28, 2005
    #3
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