coregen help

[niyander]

hello

can anyone tell me how to use coregen generated core in Xilinx - ISE
9.1i
actually i have used it to generate an 8 point fft core. But when i
synthesize it, the report says that it has used only 49 IOB out of 221
available and 0 slices out of 7680 available, i think the core is not
synthesized properly.
any help is appreciated. below is my vhdl code attached, please take a
look.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test_fft is
generic(
adder_width : positive := 24;
adder_depth : positive := 2;
adc_data_width : positive := 12;
window_ram_adr_width : positive := 8;
window_ram_data_width : positive := 12;
wola_num_blocks : positive := 4
);
port (
CLK, RST : in std_logic;
FFT_XK_RE : out std_logic_vector(15 downto 0);
FFT_XK_IM : out std_logic_vector(15 downto 0);
ADC_DATA: in std_logic_vector(15 downto 0)
);
end test_fft;


architecture Behavioral of test_fft is
component fft_8
port (
xn_re: IN std_logic_VECTOR(15 downto 0);
xn_im: IN std_logic_VECTOR(15 downto 0);
start: IN std_logic;
fwd_inv: IN std_logic;
fwd_inv_we: IN std_logic;
clk: IN std_logic;
xk_re: OUT std_logic_VECTOR(15 downto 0);
xk_im: OUT std_logic_VECTOR(15 downto 0);
xn_index: OUT std_logic_VECTOR(5 downto 0);
xk_index: OUT std_logic_VECTOR(5 downto 0);
rfd: OUT std_logic;
busy: OUT std_logic;
dv: OUT std_logic;
edone: OUT std_logic;
done: OUT std_logic);
end component;

begin
FFT: fft_8
port map (
xn_re => ADC_DATA,
xn_im => ADC_DATA,
start => '1',
fwd_inv => '1',
fwd_inv_we => '0',
clk => CLK,
xk_re => FFT_XK_RE,
xk_im => FFT_XK_IM,
xn_index => open,
xk_index => open,
rfd => open,
busy => open,
dv => open,
edone => open,
done => open);

end Behavioral;

thanks

 

[Jim]

hello

can anyone tell me how to use coregen generated core in Xilinx - ISE
9.1i
actually i have used it to generate an 8 point fft core. But when i
synthesize it, the report says that it has used only 49 IOB out of 221
available and 0 slices out of 7680 available, i think the core is not
synthesized properly.
any help is appreciated. below is my vhdl code attached, please take a
look.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity test_fft is
generic(
adder_width : positive := 24;
adder_depth : positive := 2;
adc_data_width : positive := 12;
window_ram_adr_width : positive := 8;
window_ram_data_width : positive := 12;
wola_num_blocks : positive := 4
);
port (
CLK, RST : in std_logic;
FFT_XK_RE : out std_logic_vector(15 downto 0);
FFT_XK_IM : out std_logic_vector(15 downto 0);
ADC_DATA: in std_logic_vector(15 downto 0)
);
end test_fft;

architecture Behavioral of test_fft is
component fft_8
port (
xn_re: IN std_logic_VECTOR(15 downto 0);
xn_im: IN std_logic_VECTOR(15 downto 0);
start: IN std_logic;
fwd_inv: IN std_logic;
fwd_inv_we: IN std_logic;
clk: IN std_logic;
xk_re: OUT std_logic_VECTOR(15 downto 0);
xk_im: OUT std_logic_VECTOR(15 downto 0);
xn_index: OUT std_logic_VECTOR(5 downto 0);
xk_index: OUT std_logic_VECTOR(5 downto 0);
rfd: OUT std_logic;
busy: OUT std_logic;
dv: OUT std_logic;
edone: OUT std_logic;
done: OUT std_logic);
end component;

begin
FFT: fft_8
port map (
xn_re => ADC_DATA,
xn_im => ADC_DATA,
start => '1',
fwd_inv => '1',
fwd_inv_we => '0',
clk => CLK,
xk_re => FFT_XK_RE,
xk_im => FFT_XK_IM,
xn_index => open,
xk_index => open,
rfd => open,
busy => open,
dv => open,
edone => open,
done => open);

end Behavioral;

thanks

I think the fft core is treated as a blackbox by the synthesizer. It
doesn't count the logic inside blackbox, instead it should report an
FFT core under the logic utilization.

Cheers,
Jim
http://myfpgablog.blogspot.com/