Count = Count + 1 Using only std_logic_1164 Doubt

Discussion in 'VHDL' started by efelnavarro09, Jan 24, 2011.

  1. efelnavarro09

    efelnavarro09

    Joined:
    Jan 24, 2011
    Messages:
    2
    Hello I'm new in this forum and recently I received an assigment for my Digital Systems Class. Its common to use in C/C++ or any high level language, a notation like cont = cont + 1. But my professor has prohibited the use of any library but std_logic_1164. I need to run a count of 32-bit and I have a component that can sum 32-bit, but I don't have any idea of how to perform it. Normally I will use

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    ...
    signal tmp : std_logic_vector(31 downto 0);
    process(clk, rst)
    begin
    ...
    if tmp >= x"FFFFFFFF" then
    tmp <= x"00000000";
    else
    tmp <= tmp + '1';
    end if;
    ...

    But I can't do that, at the moment I have something like

    library ieee;
    use ieee.std_logic_1164.all;
    ...
    signal tmp, tmp2 : std_logic_vector(31 downto 0);
    signal caux : std_logic;

    component fullAdder32 is port(
    a32, b32 : in std_logic_vector(31 downto 0);
    s32 : out std_logic_vector(31 downto 0);
    cout : out std_logic);
    end component;

    begin

    f32 : fullAdder32 port map (tmp, 0x"00000001", tmp2, caux);

    process(clk, rst)
    begin
    ...
    if tmp >= x"FFFFFFFF" then
    tmp <= x"00000000";
    else
    tmp <= tmp2;
    end if;

    Is there a correct way to perform that because my code "compile" but with the instruction of "tmp <= tmp2" give a report of 100 macrocells and I only have 64 in the CPLD (Altera MAX3000). Without that instruction the fitter shows 20/64. Using, tmp = tmp + '1', the fitter shows (67/64). So I will appreciate any advice or sample you can show. Thanks in advance
    efelnavarro09, Jan 24, 2011
    #1
    1. Advertising

  2. efelnavarro09

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    Increment can be implemented in a simpler way then the general addition;
    In pseudo code:

    Code:
      i := 0;
      incr := tmp;
      while(tmp(i) = '1') loop
        incr(i) := '0';
        i := i + 1;
      end loop;
      -- tmp(i) '0' -> '1'
      incr(i) := '1';
    
    I'm not really certain whether this can be made to synthesize in something smaller though;

    Anyway another way is only handle one bit or a few bits in one clock cycle (spreading the overall addition over 4 cycles of 4-bit additions for example)
    That's the common trade off, size vs speed ofcourse
    joris, Jan 24, 2011
    #2
    1. Advertising

  3. efelnavarro09

    efelnavarro09

    Joined:
    Jan 24, 2011
    Messages:
    2
    Hello joris, thanks for your reply.

    Finally I solved using half adders, next is a test code for a clock division.
    library ieee;
    use ieee.std_logic_1164.all;
    entity clkdiv is
    port(

    sysclk : in std_logic;
    sysrst : in std_logic;
    clkdiv : out std_logic

    );
    end entity;

    architecture arch of clkdiv is

    component halfAdder is
    port(

    ah : in std_logic;
    bh : in std_logic;
    sh : out std_logic;
    ch : out std_logic;

    );
    end component;
    signal cnt : std_logic_vector(3 downto 0);
    signal cn1 : std_logic_vector(3 downto 0);
    signal carr : std_logic_vector(3 downto 1);
    signal tmp : std_logic;

    begin

    h0: halfAdder port map(cnt(0), '1', cn1(0), carr(1));
    h1: halfAdder port map(cnt(1), carr(1), cn1(1), carr(2));
    h2: halfAdder port map(cnt(2), carr(2), cn1(2), carr(3));
    cn1(3) <= cnt(3) xor carr(3);

    process(sysclk, sysrst)

    constant clow : std_logic_vector(3 downto 0) := x"7";
    constant chigh : std_logic_vector(3 downto 0) := x"F";

    begin

    if sysrst = '0' then

    cnt <= x"0";

    elsif sysclk = '1' and sysclk'event then

    cnt <= cn1;
    if cnt < clow then
    tmp <= '0';
    elsif cnt >= clow and cnt < chigh then
    tmp <= '1';
    else
    cnt <= x"0";
    end if;

    end if;

    clkdiv <= tmp;

    end process;

    end architecture;
    efelnavarro09, Jan 26, 2011
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. drseek@email.com
    Replies:
    0
    Views:
    804
    drseek@email.com
    May 16, 2006
  2. Nikos
    Replies:
    5
    Views:
    2,274
  3. aijazbaig1@gmail.com

    Compiler can't detect std_logic_1164 package

    aijazbaig1@gmail.com, Aug 11, 2006, in forum: VHDL
    Replies:
    15
    Views:
    875
    Mike Treseler
    Aug 17, 2006
  4. Diego UTN-FRP
    Replies:
    4
    Views:
    4,472
    Diego UTN-FRP
    Nov 29, 2009
  5. delightfulbaker
    Replies:
    3
    Views:
    1,612
    julianm
    Jul 29, 2011
Loading...

Share This Page