counter plus comparator

[john]

Hello,

My 19 bit up counter is working fine but its not toggling
the "count_equal" signal. Its just keeping its value to '0'.
The comparator is not working for 19 bits but it does work for
less than 19 bits.. I am using the comparator to know that count is done!
Please advice... I am also attaching my code...

Thanks
Regards
john


Entity counter is
Port (
Qout : out unsigned (18 downto 0); -- 19 bit address bus output
Din ut unsigned (18 downto 0); -- 19 bit address bus input
DPR_CLK : in std_logic; -- Clock for the counter
P : in std_logic; -- Increment the count
count_equal: out std_logic;
Reset_c: in std_logic

);
End counter;
-------------------------------------------------------------
Architecture count_arch of counter is

Signal Q : unsigned (18 downto 0);
Signal D : unsigned ( 18 downto 0):="1111111111111111111";
Begin
Qout<=Q;

process(DPR_Clk,Reset_c)
Begin
If (Reset_c = '1') then
Q(18 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0');

count_equal <='0';

Else if (DPR_Clk='1' and DPR_Clk'event) then

If (P = '1') then
Q <= Q + 1;

count_equal <='0';

If(Q = D) Then

count_equal<='1';
Q(18 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0');
End if;
End if;
End If;
End If;
End process;
End count_arch ;

 

[Jim Lewis]

John,
Run your simulation longer. What is Q when count_equal = 1?
Perhaps you want to check with your shorter simulations.

My read of the code says that Count_Equal = 1 when Q = 0.
Going further it looks like Q will be 0 for two clocks.
You have some debugging to do.

Hints:
* Signals do not get updated immediately when they are
assigned - they get their value a simulation cycle
(delta cycle) later. This is the why behind your
current behavior.
* All signal assignments in a clocked process create
registers, hence, count_equal, has a register on it.
If you want the register there (often a good thing),
then you need to adjust your end detect value.

Question: Is Count_Equal allowed to be 1 when P is not 1?

Code/hardware improvement notes:
* If you are counting 2**n values, you can let the counter
roll-over on its own, rather than specify it in your code.
* Use "elsif" rather than "else if" and you can skip one
the "end if;"

* Rather than:
Q(18 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0');

You could write:
Q <= (others => '0') ;
-- or --
Q <= "000000000000000000";
-- or --
Q <= to_unsigned(0,19) ;

If your text book is encouraging you to code like your wrote
above, get J. Bhasker's "A VHDL Primer".


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[john]

Thanks very much for ur reply! I did follow your advices but the reult
is same..
I reduced the counter to 5 bit counter( everything is same) and it did
work fine.. Would you please like to comment!
Regards
john

 

[Jim Lewis]

John,
I go back to my original statement:
Run your simulation longer.

You need to run for 2**19 clocks where P = 1.
If P is 1 every other clock, that means you need
to run for a little more than 1 million clocks.

I ran this and it seems to work fine.
It seems that perhaps you don't have any debugging.

Cheers,
Jim

 

[Raghavendra]

Hello,

My 19 bit up counter is working fine but its not toggling
the "count_equal" signal. Its just keeping its value to '0'.
The comparator is not working for 19 bits but it does work for
less than 19 bits.. I am using the comparator to know that count is done!
Please advice... I am also attaching my code...

Thanks
Regards
john


Entity counter is
Port (
Qout : out unsigned (18 downto 0); -- 19 bit address bus output
Din ut unsigned (18 downto 0); -- 19 bit address bus input
DPR_CLK : in std_logic; -- Clock for the counter
P : in std_logic; -- Increment the count
count_equal: out std_logic;
Reset_c: in std_logic

);
End counter;
-------------------------------------------------------------
Architecture count_arch of counter is

Signal Q : unsigned (18 downto 0);
Signal D : unsigned ( 18 downto 0):="1111111111111111111";
Begin
Qout<=Q;

process(DPR_Clk,Reset_c)
Begin
If (Reset_c = '1') then
Q(18 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0');

count_equal <='0';

Else if (DPR_Clk='1' and DPR_Clk'event) then

If (P = '1') then
Q <= Q + 1;

count_equal <='0';

If(Q = D) Then

count_equal<='1';
Q(18 downto 0) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0');
End if;
End if;
End If;
End If;
End process;
End count_arch ;

Hi,
You need not force Q to zero when Q=D..
U perform Q = Q + 1 in the else part of "if(Q=d) then" statement.
I still u do not get reslut.U replace D with "1111..11"'s.may be D is
not initialized.

Raghavendra.Sortur