Counter simulation proper but giving trouble in DFT

[nisheethg]

The following code generates the following series for TC = 5
CNTR : 1 2 3 4 5
TC_MINUS_CNTR: 6 5 4 3 2

counter increments when CNTR_INCR is HIGH
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity su_pixel_counter is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
EN : in STD_LOGIC;
CNTR_INCR : in STD_LOGIC;
LOAD_PIXEL : in STD_LOGIC;
TC : in STD_LOGIC_VECTOR( 3 downto 0);
COUNT_ONE : out STD_LOGIC;
COUNT_ONE_IF_INCR : out STD_LOGIC;-- First Count i.e. zero
CNTR : out STD_LOGIC_VECTOR ( 3 downto 0);
TC_MINUS_CNTR : out STD_LOGIC_VECTOR ( 3 downto 0);
SUM_OF_CNTR_AND_TC_MINUS_CNTR: out STD_LOGIC_VECTOR ( 3 downto 0);
PIXEL_CNTR_COUNT_OVER : out STD_LOGIC

--test
);
end su_pixel_counter;

architecture Behavioral of su_pixel_counter is

SIGNAL CNTR_IN : STD_LOGIC_VECTOR(3 downto 0); -- original value 1
begin

process(CLK, RESET)
begin

if ( RESET ='1') then
CNTR_IN <= b"0000";
PIXEL_CNTR_COUNT_OVER <= '0';
COUNT_ONE_IF_INCR <= '0';


elsif(CLK'event and CLK ='1') then
if ( EN ='1') then
if (CNTR_INCR = '1') then


if ( CNTR_IN = "0000") then
COUNT_ONE_IF_INCR<= '1';
PIXEL_CNTR_COUNT_OVER <= '0';
CNTR_IN <= CNTR_IN + 1;

elsif ( CNTR_IN = TC) then
COUNT_ONE_IF_INCR<= '0';
PIXEL_CNTR_COUNT_OVER <= '1';
CNTR_IN <= CNTR_IN + 1;

elsif ( CNTR_IN = TC + 1 ) then
COUNT_ONE_IF_INCR<= '0';
PIXEL_CNTR_COUNT_OVER <= '0';
CNTR_IN <= b"0000";
else
CNTR_IN <= CNTR_IN + 1;

end if;



end if;

else
PIXEL_CNTR_COUNT_OVER<= '0';
COUNT_ONE_IF_INCR<= '0';
end if;

CNTR<= CNTR_IN;
TC_MINUS_CNTR<= (TC + 2) - CNTR_IN;
SUM_OF_CNTR_AND_TC_MINUS_CNTR <= TC + 2;


end if;
end process;


--- COunter intitial value flag
process( CLK, RESET)
begin
if (RESET ='1') then
COUNT_ONE<= '0';
elsif (CLK ='1' and CLK'event) then
if (CNTR_IN = b"0001") then
COUNT_ONE<= '1';
else
COUNT_ONE<= '0';
end if;
end if;
end process;

end Behavioral;
--------------------------------------------------------------------------------------------------------------------------
during DFT

Warning: Asynchronous pins of cell calcUnit_1/su/SU_pc/CNTR_IN_reg[2]
(R_SDFFPRX2) are uncontrollable. (TEST-116)
Warning: Asynchronous pins of cell calcUnit_1/su/SU_pc/
PIXEL_CNTR_COUNT_OVER_reg (R_DFFPRX2) are uncontrollable. (TEST-116)
--------------------------------------------------------------------------------------------------------------------------


I have no clues what to do to fix these warnings...

Please help.

Thanks.

Regards

 

[nisheethg]

Nailed the problem !!
No prob with the code i posted !!
I mixed sync and async reset while instantiating my counter in top
module