counter + somesteps

Discussion in 'VHDL' started by Rafa, Feb 4, 2004.

  1. Rafa

    Rafa Guest

    Hello to everyone. I´m new in VHDL and i have (maybe) just a simple
    question.
    There´s a counter who counts steps from a PLL.
    I want to add a special function wich makes the counter add some steps
    during a circle
    like this:




    IF (PLL'event AND PLL = '1') THEN

    counter <= counter + 1 + somesteps
    END IF;

    The problem:

    If there is no adjustment the somestep-Input is 0.
    If there are somesteps to add the counter adds the value of
    "somesteps" for every PLL-Edge.
    But I want to add is only one time.

    Has someone an idea?
     
    Rafa, Feb 4, 2004
    #1
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  2. Rafa wrote:


    > IF (PLL'event AND PLL = '1') THEN
    >
    > counter <= counter + 1 + somesteps
    > END IF;
    >
    > The problem:
    >
    > If there is no adjustment the somestep-Input is 0.
    > If there are somesteps to add the counter adds the value of
    > "somesteps" for every PLL-Edge.
    > But I want to add is only one time.



    I'm not sure, if I understand you right, but what about:


    IF (PLL'event AND PLL = '1') THEN
    if (adjustment='1') then
    counter <= counter + somesteps + 1;
    else
    counter <= counter + 1;
    end if;
    END IF;

    Signal adjustment has to be updated before next rising_edge(PLL),
    whether somesteps has to be added or not.


    The above code will synthesize as a half adder (full adder with constant
    "somesteps" input) and carry_in.

    Ralf
     
    Ralf Hildebrandt, Feb 4, 2004
    #2
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  3. Rafa

    Rafael. N Guest

    Am Wed, 04 Feb 2004 16:26:23 +0100 schrieb Ralf Hildebrandt
    <>:

    > Rafa wrote:
    >
    >
    >> IF (PLL'event AND PLL = '1') THEN
    >>
    >> counter <= counter + 1 + somesteps END IF;
    >>
    >> The problem:
    >>
    >> If there is no adjustment the somestep-Input is 0.
    >> If there are somesteps to add the counter adds the value of
    >> "somesteps" for every PLL-Edge.
    >> But I want to add is only one time.

    >
    >
    > I'm not sure, if I understand you right, but what about:
    >
    >
    > IF (PLL'event AND PLL = '1') THEN
    > if (adjustment='1') then
    > counter <= counter + somesteps + 1;
    > else
    > counter <= counter + 1;
    > end if;
    > END IF;
    >
    > Signal adjustment has to be updated before next rising_edge(PLL),
    > whether somesteps has to be added or not.
    >
    >
    > The above code will synthesize as a half adder (full adder with constant
    > "somesteps" input) and carry_in.
    >
    > Ralf
    >

    It´s a good idea!
    The problem is, that "adjustment" is driven by a microprocessor so that
    it has for a lot of PLL-Circles the value '1'.
    That would result in adding "somesteps" for more than one PLL-Circle.


    --
    Erstellt mit M2, Operas revolutionärem E-Mail-Modul:
    http://www.opera.com/m2/
     
    Rafael. N, Feb 4, 2004
    #3
  4. Rafael. N wrote:
    > It´s a good idea!
    > The problem is, that "adjustment" is driven by a microprocessor so that
    > it has for a lot of PLL-Circles the value '1'.
    > That would result in adding "somesteps" for more than one PLL-Circle.
    >


    I've done something like this a couple of times, but I am not entirely
    sure I am doing it the best way. I meant to look it up, but when I
    weren't encountering any serious problems, I just left it as it were.

    Please correct me, someone, if this is crap. I am sort of a newbie.

    Anyway, what I'm doing is this:


    if (PLL'event and PLL = '1') then
    if (adjustment = '1' and adj_old = '0') then
    counter <= counter + somesteps + 1;
    adj_old = '1';
    elsif (adjustment = '0')
    counter <= counter + 1;
    adj_old <= '0';
    else
    counter <= counter + 1;
    adj_old <= adj_old; -- To avoid latch.
    end if;
    end if;


    This would of course only work, if you can be sure that the ajustment
    signal doesn't go low and high between PLL events.

    Have you considered the posibillity of making this a clocked process?
    That would make things a lot easier, then you just implement it as a
    statemachine and make the clock run fast enough to be absolutely sure
    that adjustment is high more than one cycle.

    -- Anders
     
    Anders Hellerup Madsen, Feb 4, 2004
    #4
  5. Rafa

    Sajan Guest

    May be this will help

    if (PLL'event and PLL = '1') then
    if (adjustment = '1' and adj_old = '0') then
    counter <= counter + somesteps + 1;
    else
    counter <= counter + 1;
    end if;
    adj_old <= adjustment;
    end if;


    Cheers,
    Sajan.

    Anders Hellerup Madsen <> wrote in message news:<bvredb$22h$-c.dk>...
    > Rafael. N wrote:
    > > It´s a good idea!
    > > The problem is, that "adjustment" is driven by a microprocessor so that
    > > it has for a lot of PLL-Circles the value '1'.
    > > That would result in adding "somesteps" for more than one PLL-Circle.
    > >

    >
    > I've done something like this a couple of times, but I am not entirely
    > sure I am doing it the best way. I meant to look it up, but when I
    > weren't encountering any serious problems, I just left it as it were.
    >
    > Please correct me, someone, if this is crap. I am sort of a newbie.
    >
    > Anyway, what I'm doing is this:
    >
    >
    > if (PLL'event and PLL = '1') then
    > if (adjustment = '1' and adj_old = '0') then
    > counter <= counter + somesteps + 1;
    > adj_old = '1';
    > elsif (adjustment = '0')
    > counter <= counter + 1;
    > adj_old <= '0';
    > else
    > counter <= counter + 1;
    > adj_old <= adj_old; -- To avoid latch.
    > end if;
    > end if;
    >
    >
    > This would of course only work, if you can be sure that the ajustment
    > signal doesn't go low and high between PLL events.
    >
    > Have you considered the posibillity of making this a clocked process?
    > That would make things a lot easier, then you just implement it as a
    > statemachine and make the clock run fast enough to be absolutely sure
    > that adjustment is high more than one cycle.
    >
    > -- Anders
     
    Sajan, Feb 5, 2004
    #5
  6. Sajan wrote:
    > May be this will help
    >
    > if (PLL'event and PLL = '1') then
    > if (adjustment = '1' and adj_old = '0') then
    > counter <= counter + somesteps + 1;
    > else
    > counter <= counter + 1;
    > end if;
    > adj_old <= adjustment;
    > end if;


    Yeah, that looks a lot smoother than my solution. If I were Rafa, I'd
    hang on to that one.

    -- Anders
     
    Anders Hellerup Madsen, Feb 5, 2004
    #6
  7. Rafa

    Rafa Guest

    My special problem was that i wanted to add somesteps allways.
    - sometimes within data sometimes without (somesteps <= 0)
    ..... i didn´t want to chance the state-machine that exist in my previous code.
    I solved it now this way.

    adj: PROCESS (Inp_Time_Flag,PLL)
    BEGIN
    IF Inp_Time_Flag = '0' Then
    T_counter <= 0;
    somesteps <= (others =>'0');

    ELSE
    IF T_counter < 4 THEN
    IF PLL'event AND PLL = '1' THEN

    CASE T_Counter IS
    WHEN 1 => somesteps <= (Inp_Sec);
    WHEN others => somesteps <= (others =>'0');
    END CASE;

    T_counter <= T_counter + 1;

    END IF;
    END IF;
    END IF;
    END PROCESS adj;

    I don´t know if this is "clean" code - but it works.
    If someone could comment this solution....?!
     
    Rafa, Feb 5, 2004
    #7
  8. Rafa wrote:

    > adj: PROCESS (Inp_Time_Flag,PLL)
    > BEGIN
    > IF Inp_Time_Flag = '0' Then
    > T_counter <= 0;
    > somesteps <= (others =>'0');
    >
    > ELSE
    > IF T_counter < 4 THEN
    > IF PLL'event AND PLL = '1' THEN


    'event detection inside an if-statement is not allowed for synthesis.
    Just exchange the order:

    IF PLL'event AND PLL = '1' THEN
    IF T_counter < 4 THEN

    .... and make sure, that the behavior is o.k. for you.


    >
    > CASE T_Counter IS
    > WHEN 1 => somesteps <= (Inp_Sec);
    > WHEN others => somesteps <= (others =>'0');
    > END CASE;


    O.k. here somesteps are flipflops following a mux.

    When adding somesteps to an other value this adder will be a full adder.


    Ralf
     
    Ralf Hildebrandt, Feb 5, 2004
    #8
  9. Rafa

    Rafa Guest

    OK - it works!!!!!!!
    -- thanks a lot to all of you..

    Regards Rafa
     
    Rafa, Feb 7, 2004
    #9
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