Counter with initial value

Discussion in 'VHDL' started by Obtice, Nov 21, 2011.

  1. Obtice

    Obtice

    Joined:
    Nov 10, 2011
    Messages:
    9
    Hi,
    I have a counter written in VHDL :

    Code:
    Library IEEE;
    use ieee.std_logic_1164.all;
    --use ieee.numeric_std.all;
    
    Entity counter is
        port
        (
            clk        : in std_logic;
            reset    : in std_logic;
            enable     : in std_logic;
            q        : out integer range 0 to 255
        );
    end counter;
    Architecture count of counter is
    begin
        process (clk)
            variable   cnt    : integer range 0 to 255;
        begin
            if (rising_edge(clk)) then
                if reset = '1' then
                    cnt := 0;
                elsif enable = '1' then
                    cnt := cnt + 1;
                end if;
            end if;
            q <= cnt;
        end process;
    end count;
    
    How can I edit this code, so that it starts to count from 50,
    50, 51, 52,53 ......

    thanks in advance ....
    Obtice, Nov 21, 2011
    #1
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  2. Obtice

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Counter

    You have a number of options to accomplish this; among these are:

    You can set the count to 50 instead of 0 on reset.

    You can have a new load input that sets the count to 50 when asserted.
    eliascm, Nov 21, 2011
    #2
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  3. Obtice

    Obtice

    Joined:
    Nov 10, 2011
    Messages:
    9
    thanks,
    first solution worked,

    Code:
    Library IEEE;
    use ieee.std_logic_1164.all;
    
    Entity counter is
        port
        (
            clk        : in std_logic;
            reset    : in std_logic;
            enable     : in std_logic;
            q        : out integer range 0 to 255
        );
    end counter;
    Architecture count of counter is
    begin
        process (clk)
            variable   cnt    : integer range 0 to 255;
        begin
            if (rising_edge(clk)) then
                if reset = '1' then
                    cnt := 50;
                elsif enable = '1' then
                    cnt := cnt + 1;
                end if;
            end if;
            q <= cnt;
        end process;
    end count;
    
    but about the second. A bit more tips .... please .
    Obtice, Nov 21, 2011
    #3
  4. Obtice

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    I think the second option would look similar to this:
    Code:
    Library IEEE;
    use ieee.std_logic_1164.all;
    --use ieee.numeric_std.all;
    
    Entity counter is
        port
        (
            clk        : in std_logic;
            reset    : in std_logic;
            enable     : in std_logic;
            load : in std_logic;
            p: in integer  range 0 to 255
            q        : out integer range 0 to 255
        );
    end counter;
    Architecture count of counter is
    begin
        process (clk)
            variable   cnt    : integer range 0 to 255;
        begin
            if (rising_edge(clk)) then
                if reset = '1' then
                    cnt := 50;
                elsif enable = '1' then
                    if load = '1' then
                      cnt := p;
                    else
                    cnt := cnt + 1;
                    end if;
                end if;
            end if;
            q <= cnt;
        end process;
    end count;
    joris, Nov 24, 2011
    #4
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