CRC calculation

Discussion in 'VHDL' started by edi.fraiman@gmail.com, Feb 16, 2007.

  1. Guest

    Hi,

    In my design FPGA is between MAC and PHY. I have to change frame
    payload and recalculate CRC. I calculate CRC over the destination
    address + source address+ length/type +new data+ pad.

    I am using Ethereal SW in order capture frame. So I am trying to
    calculate CRC on original frame (without changing data) and compare to
    what captured by Ethereal.
    But it's never same (also even result is inverted and reflected)

    Here is VHDL code.
    ---------------------------------------------------------------------------------------------------
    entity crc_gen is
    port ( crc : out STD_LOGIC_VECTOR (31 downto 0);
    d_in : in STD_LOGIC_VECTOR (3 downto 0);
    clk,en,nPOR,MAC_MII_TXEN : in std_logic);
    end crc_gen;

    architecture Behavioral of crc_gen is
    --
    signal NewCRC : STD_LOGIC_VECTOR(31 downto 0);
    signal OldCRC : STD_LOGIC_VECTOR(31 downto 0);
    --
    begin
    NewCRC(0) <= d_in(0) xor OldCRC(28);
    NewCRC(0) <= d_in(0) xor OldCRC(28);
    NewCRC(1) <= d_in(1) xor d_in(0) xor OldCRC(28) xor OldCRC(29);
    NewCRC(2) <= d_in(2) xor d_in(1) xor d_in(0) xor OldCRC(28) xor
    OldCRC(29) xor OldCRC(30);
    NewCRC(3) <= d_in(3) xor d_in(2) xor d_in(1) xor OldCRC(29) xor
    OldCRC(30) xor OldCRC(31);
    NewCRC(4) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(0) xor
    OldCRC(28) xor OldCRC(30) xor
    OldCRC(31);
    NewCRC(5) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(1) xor
    OldCRC(28) xor OldCRC(29) xor
    OldCRC(31);
    NewCRC(6) <= d_in(2) xor d_in(1) xor OldCRC(2) xor OldCRC(29) xor
    OldCRC(30);
    NewCRC(7) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(3) xor
    OldCRC(28) xor OldCRC(30) xor
    OldCRC(31);
    NewCRC(8) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(4) xor
    OldCRC(28) xor OldCRC(29) xor
    OldCRC(31);
    NewCRC(9) <= d_in(2) xor d_in(1) xor OldCRC(5) xor OldCRC(29) xor
    OldCRC(30);
    NewCRC(10) <= d_in(3) xor d_in(2) xor d_in(0) xor OldCRC(6) xor
    OldCRC(28) xor OldCRC(30) xor
    OldCRC(31);
    NewCRC(11) <= d_in(3) xor d_in(1) xor d_in(0) xor OldCRC(7) xor
    OldCRC(28) xor OldCRC(29) xor
    OldCRC(31);
    NewCRC(12) <= d_in(2) xor d_in(1) xor d_in(0) xor OldCRC(8) xor
    OldCRC(28) xor OldCRC(29) xor
    OldCRC(30);
    NewCRC(13) <= d_in(3) xor d_in(2) xor d_in(1) xor OldCRC(9) xor
    OldCRC(29) xor OldCRC(30) xor
    OldCRC(31);
    NewCRC(14) <= d_in(3) xor d_in(2) xor OldCRC(10) xor OldCRC(30)
    xor OldCRC(31);
    NewCRC(15) <= d_in(3) xor OldCRC(11) xor OldCRC(31);
    NewCRC(16) <= d_in(0) xor OldCRC(12) xor OldCRC(28);
    NewCRC(17) <= d_in(1) xor OldCRC(13) xor OldCRC(29);
    NewCRC(18) <= d_in(2) xor OldCRC(14) xor OldCRC(30);
    NewCRC(19) <= d_in(3) xor OldCRC(15) xor OldCRC(31);
    NewCRC(20) <= OldCRC(16);
    NewCRC(21) <= OldCRC(17);
    NewCRC(22) <= d_in(0) xor OldCRC(18) xor OldCRC(28);
    NewCRC(23) <= d_in(1) xor d_in(0) xor OldCRC(19) xor OldCRC(28)
    xor OldCRC(29);
    NewCRC(24) <= d_in(2) xor d_in(1) xor OldCRC(20) xor OldCRC(29)
    xor OldCRC(30);
    NewCRC(25) <= d_in(3) xor d_in(2) xor OldCRC(21) xor OldCRC(30)
    xor OldCRC(31);
    NewCRC(26) <= d_in(3) xor d_in(0) xor OldCRC(22) xor OldCRC(28)
    xor OldCRC(31);
    NewCRC(27) <= d_in(1) xor OldCRC(23) xor OldCRC(29);
    NewCRC(28) <= d_in(2) xor OldCRC(24) xor OldCRC(30);
    NewCRC(29) <= d_in(3) xor OldCRC(25) xor OldCRC(31);
    NewCRC(30) <= OldCRC(26);
    NewCRC(31) <= OldCRC(27);
    --
    process (clk)
    begin
    if rising_edge (clk) then
    if (nPOR = '0' or MAC_MII_TXEN = '0') then
    OldCRC <= (others => '1');
    elsif (en = '1') then
    OldCRC <= NewCRC;
    else
    null;
    end if;
    end if;
    end process;
    --
    crc <= OldCRC;
    --
    end Behavioral;
    ---------------------------------------------

    Could somebody help me?

    Best regards,
    Edi Fraiman
    , Feb 16, 2007
    #1
    1. Advertising

  2. wrote:

    > In my design FPGA is between MAC and PHY. I have to change frame
    > payload and recalculate CRC. I calculate CRC over the destination
    > address + source address+ length/type +new data+ pad.
    >
    > I am using Ethereal SW in order capture frame. So I am trying to
    > calculate CRC on original frame (without changing data) and compare to
    > what captured by Ethereal.
    > But it's never same (also even result is inverted and reflected)


    There are lots of ways to get this wrong.
    Start googling here:
    http://groups.google.com/groups/search?q=crc_shift

    > Here is VHDL code.


    I would run a sim and do some debugging
    to obtain a specific question to ask here.
    Good luck.

    -- Mike Treseler
    Mike Treseler, Feb 16, 2007
    #2
    1. Advertising

  3. wrote:
    >
    > Could somebody help me?


    Check out http://www.easics.com/webtools/crctool

    Using that, you "just" have to sort out the right bit/byte order and
    initialization. Do a simulation with a known good ethernet frame. If
    I remember correctly, some known good frames can be found in the IEEE
    standard.

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
    Paul Uiterlinden, Feb 17, 2007
    #3
  4. Paul Uiterlinden <> writes:

    > wrote:
    >>
    >> Could somebody help me?

    >
    > Check out http://www.easics.com/webtools/crctool
    >
    > Using that, you "just" have to sort out the right bit/byte order and
    > initialization. Do a simulation with a known good ethernet frame. If
    > I remember correctly, some known good frames can be found in the IEEE
    > standard.


    Affirmative. There are some in Annex 36A.4 and 36A.5 at least.

    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
    Kai Harrekilde-Petersen, Feb 18, 2007
    #4
  5. writes:
    > But it's never same (also even result is inverted and reflected)


    I'd suggest consulting the standard. Things are a bit confusing,
    indeed.

    ,----[ IEEE 802.3, 2000 Edition, p41 ]
    | The bits of the CRC are thus transmitted in the order x^31,
    | x^30,...,x^1,x^0.
    `----

    Which incidentially is the opposite order of all other data in a
    frame.

    -- Marcus
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    -- Michael McNamara
    (http://www.veripool.com/verilog-mode_news.html)
    Marcus Harnisch, Feb 26, 2007
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Runar Gjelsvik

    CRC polynomal calculation

    Runar Gjelsvik, Apr 28, 2004, in forum: VHDL
    Replies:
    2
    Views:
    2,264
    Allan Herriman
    Apr 29, 2004
  2. subscribe
    Replies:
    3
    Views:
    4,144
    Chris Uppal
    Nov 29, 2006
  3. Mamut

    crc-8 and crc-16 code...

    Mamut, Feb 21, 2007, in forum: C++
    Replies:
    5
    Views:
    4,015
    Victor Bazarov
    Feb 22, 2007
  4. `Zidane Tribal
    Replies:
    1
    Views:
    2,500
    Joe Smith
    Jul 28, 2007
  5. `Zidane Tribal
    Replies:
    3
    Views:
    235
    Sisyphus
    Jul 27, 2007
Loading...

Share This Page