Recently we wrote a synthesizable CRC package. Feel free to add your
generator polys
-------------------------------------------------------------------------------
-- Title : CRC Package
-- Project :
-------------------------------------------------------------------------------
-- File : crc_pack.vhd
-- Author : DI. R. Hecht <
[email protected]>
-- Company :
-- Created : 2003-04-23
-- Last update: 2003-07-28
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Provides two functions to calculate the next CRC value. One
-- function takes a single bit as next data, and the other one
-- processes more than one bit.
--
-- Common generator polynomials are provided too.
--
-- General usage:
-- fcs := initial;
-- for i in ... loop
-- fcs := next_crc(fcs, data, CRC32_GEN);
-- end loop;
-------------------------------------------------------------------------------
-- Copyright (c) 2003
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2003-04-23 1.0 hr55 Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package crc_pack is
-----------------------------------------------------------------------------
-- CRC functions
-----------------------------------------------------------------------------
-- calculates next crc value, single data bit
function next_crc (
crc : std_logic_vector; -- current CRC value
data : std_logic; -- incoming data, single bit
gen : std_logic_vector) -- generator Polynom without x^n
return std_logic_vector;
-- calculates next crc value, data vector
function next_crc (
crc : std_logic_vector; -- current CRC value
data : std_logic_vector; -- incoming data
gen : std_logic_vector) -- generator Polynom without x^n
return std_logic_vector;
-----------------------------------------------------------------------------
-- Generator polynomials
--
-- LSB represents x^0, MSB represents x^(n-1)
-- x^n is always present and thus NOT included in this representation
-----------------------------------------------------------------------------
-- CRC64 Generator: "CRC-64", ISO 3309 standard
constant CRC64_GEN : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000011011";
-- CRC32 Generator: "CRC-32", Ethernet, AAL5
constant CRC32_GEN : std_logic_vector(31 downto 0) :=
"00000100110000010001110110110111";
-- CRC16 Generator: "CRC-16", USB Data
constant CRC16_GEN : std_logic_vector(15 downto 0) := "1000000000000101";
-- CRC16 Generator: "CRC-CCITT"
constant CRC_CCITT_GEN : std_logic_vector(15 downto 0) :=
"0001000000100001";
-- CRC12 Generator: "CRC-12"
constant CRC12_GEN : std_logic_vector(11 downto 0) := "100000001111";
-- CRC10 Generator: "CRC-10", AAL 3/4, OAM
constant CRC10_GEN : std_logic_vector(9 downto 0) := "1000110011";
-- CRC8 Generator: ATM HEC
constant CRC8_GEN : std_logic_vector(7 downto 0) := "00000111";
-- CRC5 Generator: USB Token
constant CRC5_GEN : std_logic_vector(4 downto 0) := "00101";
end crc_pack;
package body crc_pack is
function next_crc (
crc : std_logic_vector;
data : std_logic;
gen : std_logic_vector)
return std_logic_vector is
begin
if (crc(crc'left) xor data) = '1' then
return (crc(crc'left - 1 downto crc'right) & '0') xor gen;
else
return (crc(crc'left - 1 downto crc'right) & '0');
end if;
end next_crc;
function next_crc (
crc : std_logic_vector;
data : std_logic_vector;
gen : std_logic_vector)
return std_logic_vector is
variable temp : std_logic_vector(crc'range);
begin
temp := crc;
for i in data'left downto data'right loop
temp := next_crc(temp, data(i), gen);
end loop; -- i
return temp;
end next_crc;
end crc_pack;
