CRC

Discussion in 'VHDL' started by Runar Gjelsvik, May 10, 2004.

  1. Hi,

    I tested the CRC tool at http://www.easics.be/webtools/crctool,
    but I was wondering about the C variable.
    Is this a variable containing the polynomial? Otherwise I don't understand
    what sort bits it consist of....
    Runar Gjelsvik, May 10, 2004
    #1
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  2. On Mon, 10 May 2004 13:35:10 +0200, "Runar Gjelsvik"
    <> wrote:

    >Hi,
    >
    >I tested the CRC tool at http://www.easics.be/webtools/crctool,
    >but I was wondering about the C variable.
    >Is this a variable containing the polynomial? Otherwise I don't understand
    >what sort bits it consist of....


    Note: C is a copy of the CRC argument to the function.

    function nextCRC32_D8
    ( Data: std_logic_vector(7 downto 0);
    CRC: std_logic_vector(31 downto 0) )
    return std_logic_vector is

    The CRC argument is the current value of the CRC register. The value
    returned by the function is the next value of the CRC register, which
    will be copied to the current value on the next clock *in code that
    you write* - the function doesn't do this for you.

    See here for why the function needs a CRC argument:
    http://groups.google.com/groups?threadm=

    You will probably need (to write) a mux as well, to preset the CRC
    register to a known value (probably all ones, or possibly all zeros)
    at the start of the frame.


    Here are some more threads you will probably want to read:
    http://groups.google.com/groups?threadm=

    Regards,
    Allan.
    Allan Herriman, May 10, 2004
    #2
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  3. On Mon, 10 May 2004 22:11:40 +1000, Allan Herriman
    <> wrote:

    >On Mon, 10 May 2004 13:35:10 +0200, "Runar Gjelsvik"
    ><> wrote:
    >
    >>Hi,
    >>
    >>I tested the CRC tool at http://www.easics.be/webtools/crctool,
    >>but I was wondering about the C variable.
    >>Is this a variable containing the polynomial? Otherwise I don't understand
    >>what sort bits it consist of....


    Oops, I forgot to answer your question in my last post.
    The C variable is the CRC register, which holds the state needed to
    calculate the result (the remainder). It is not the polynomial.

    The polynomial does not appear anywhere in the code explicitly,
    however it does determine the structure of the cloud of XOR
    expressions that make up the function.

    Regards,
    Allan.
    Allan Herriman, May 10, 2004
    #3
  4. I've tried out this code right here for my serial CRC:

    http://www.reed-electronics.com/ednmag/contents/images/di2553l1.txt

    I'm pretty newbie, and I can't seem to figure this one out.

    I've f.ex. set the polynomial to 10011, initial value to 0000 and in the
    simulation I have an input frame of 1101011011. With regular divison
    (xoring) this should amount to a remainder of 1110 (as in Russ' example).

    But with this code I don't get that, I think it was 1011. Why is that? Does
    it have to do with the initial value of crc frame?

    And secondly, if I was to use this in the receiving part I was thinking of
    just running the data frame in, including the crc, and get a zero reminder.
    But that's not the case?

    I've probably misunderstood something somewhere, but hope you can help.

    Cheers,

    Runar

    "Allan Herriman" <> wrote in
    message news:p...
    > On Mon, 10 May 2004 22:11:40 +1000, Allan Herriman
    > <> wrote:
    >
    > >On Mon, 10 May 2004 13:35:10 +0200, "Runar Gjelsvik"
    > ><> wrote:
    > >
    > >>Hi,
    > >>
    > >>I tested the CRC tool at http://www.easics.be/webtools/crctool,
    > >>but I was wondering about the C variable.
    > >>Is this a variable containing the polynomial? Otherwise I don't

    understand
    > >>what sort bits it consist of....

    >
    > Oops, I forgot to answer your question in my last post.
    > The C variable is the CRC register, which holds the state needed to
    > calculate the result (the remainder). It is not the polynomial.
    >
    > The polynomial does not appear anywhere in the code explicitly,
    > however it does determine the structure of the cloud of XOR
    > expressions that make up the function.
    >
    > Regards,
    > Allan.
    Runar Gjelsvik, May 12, 2004
    #4
  5. On Wed, 12 May 2004 10:47:10 +0200, "Runar Gjelsvik"
    <> wrote:

    >I've tried out this code right here for my serial CRC:
    >
    >http://www.reed-electronics.com/ednmag/contents/images/di2553l1.txt
    >
    >I'm pretty newbie, and I can't seem to figure this one out.
    >
    >I've f.ex. set the polynomial to 10011, initial value to 0000 and in the
    >simulation I have an input frame of 1101011011. With regular divison
    >(xoring) this should amount to a remainder of 1110 (as in Russ' example).
    >
    >But with this code I don't get that, I think it was 1011. Why is that? Does
    >it have to do with the initial value of crc frame?
    >
    >I've probably misunderstood something somewhere, but hope you can help.


    That code is incomplete (the missing bits are in 'crc_pkg') so it's a
    bit hard to say for sure.

    Suggested causes for failure of CRC:

    1. You have your input frame or poly bit reversed (i.e. left and
    right ends have been swapped).
    2. You have used the wrong initial value for the CRC register

    >And secondly, if I was to use this in the receiving part I was thinking of
    >just running the data frame in, including the crc, and get a zero reminder.
    >But that's not the case?


    It will always produce a known remainder. Sometimes it's zero,
    sometimes it's some magic number. It depends on the details of the
    CRC.
    The specification for the comms protocol will usually tell you what it
    is.

    Regards,
    Allan.
    Allan Herriman, May 12, 2004
    #5
  6. I've used the package too, but that wasn't the problem.
    But I figured it out.

    It was easy to get the picture from this document.

    http://www.mathpages.com/home/kmath458.htm

    But thanks anyway for your response


    Cheers,

    Runar

    "Allan Herriman" <> wrote in
    message news:...
    > On Wed, 12 May 2004 10:47:10 +0200, "Runar Gjelsvik"
    > <> wrote:
    >
    > >I've tried out this code right here for my serial CRC:
    > >
    > >http://www.reed-electronics.com/ednmag/contents/images/di2553l1.txt
    > >
    > >I'm pretty newbie, and I can't seem to figure this one out.
    > >
    > >I've f.ex. set the polynomial to 10011, initial value to 0000 and in the
    > >simulation I have an input frame of 1101011011. With regular divison
    > >(xoring) this should amount to a remainder of 1110 (as in Russ' example).
    > >
    > >But with this code I don't get that, I think it was 1011. Why is that?

    Does
    > >it have to do with the initial value of crc frame?
    > >
    > >I've probably misunderstood something somewhere, but hope you can help.

    >
    > That code is incomplete (the missing bits are in 'crc_pkg') so it's a
    > bit hard to say for sure.
    >
    > Suggested causes for failure of CRC:
    >
    > 1. You have your input frame or poly bit reversed (i.e. left and
    > right ends have been swapped).
    > 2. You have used the wrong initial value for the CRC register
    >
    > >And secondly, if I was to use this in the receiving part I was thinking

    of
    > >just running the data frame in, including the crc, and get a zero

    reminder.
    > >But that's not the case?

    >
    > It will always produce a known remainder. Sometimes it's zero,
    > sometimes it's some magic number. It depends on the details of the
    > CRC.
    > The specification for the comms protocol will usually tell you what it
    > is.
    >
    > Regards,
    > Allan.
    Runar Gjelsvik, May 12, 2004
    #6
  7. Runar Gjelsvik

    Ronald Hecht Guest

    Recently we wrote a synthesizable CRC package. Feel free to add your
    generator polys

    -------------------------------------------------------------------------------
    -- Title : CRC Package
    -- Project :
    -------------------------------------------------------------------------------
    -- File : crc_pack.vhd
    -- Author : DI. R. Hecht <-rostock.de>
    -- Company :
    -- Created : 2003-04-23
    -- Last update: 2003-07-28
    -- Platform :
    -- Standard : VHDL'87
    -------------------------------------------------------------------------------
    -- Description: Provides two functions to calculate the next CRC value. One
    -- function takes a single bit as next data, and the other one
    -- processes more than one bit.
    --
    -- Common generator polynomials are provided too.
    --
    -- General usage:
    -- fcs := initial;
    -- for i in ... loop
    -- fcs := next_crc(fcs, data, CRC32_GEN);
    -- end loop;
    -------------------------------------------------------------------------------
    -- Copyright (c) 2003
    -------------------------------------------------------------------------------
    -- Revisions :
    -- Date Version Author Description
    -- 2003-04-23 1.0 hr55 Created
    -------------------------------------------------------------------------------

    library ieee;
    use ieee.std_logic_1164.all;

    package crc_pack is


    -----------------------------------------------------------------------------
    -- CRC functions

    -----------------------------------------------------------------------------
    -- calculates next crc value, single data bit
    function next_crc (
    crc : std_logic_vector; -- current CRC value
    data : std_logic; -- incoming data, single bit
    gen : std_logic_vector) -- generator Polynom without x^n
    return std_logic_vector;

    -- calculates next crc value, data vector
    function next_crc (
    crc : std_logic_vector; -- current CRC value
    data : std_logic_vector; -- incoming data
    gen : std_logic_vector) -- generator Polynom without x^n
    return std_logic_vector;


    -----------------------------------------------------------------------------
    -- Generator polynomials
    --
    -- LSB represents x^0, MSB represents x^(n-1)
    -- x^n is always present and thus NOT included in this representation

    -----------------------------------------------------------------------------
    -- CRC64 Generator: "CRC-64", ISO 3309 standard
    constant CRC64_GEN : std_logic_vector(63 downto 0) :=
    "0000000000000000000000000000000000000000000000000000000000011011";
    -- CRC32 Generator: "CRC-32", Ethernet, AAL5
    constant CRC32_GEN : std_logic_vector(31 downto 0) :=
    "00000100110000010001110110110111";
    -- CRC16 Generator: "CRC-16", USB Data
    constant CRC16_GEN : std_logic_vector(15 downto 0) := "1000000000000101";
    -- CRC16 Generator: "CRC-CCITT"
    constant CRC_CCITT_GEN : std_logic_vector(15 downto 0) :=
    "0001000000100001";
    -- CRC12 Generator: "CRC-12"
    constant CRC12_GEN : std_logic_vector(11 downto 0) := "100000001111";
    -- CRC10 Generator: "CRC-10", AAL 3/4, OAM
    constant CRC10_GEN : std_logic_vector(9 downto 0) := "1000110011";
    -- CRC8 Generator: ATM HEC
    constant CRC8_GEN : std_logic_vector(7 downto 0) := "00000111";
    -- CRC5 Generator: USB Token
    constant CRC5_GEN : std_logic_vector(4 downto 0) := "00101";

    end crc_pack;

    package body crc_pack is

    function next_crc (
    crc : std_logic_vector;
    data : std_logic;
    gen : std_logic_vector)
    return std_logic_vector is
    begin
    if (crc(crc'left) xor data) = '1' then
    return (crc(crc'left - 1 downto crc'right) & '0') xor gen;
    else
    return (crc(crc'left - 1 downto crc'right) & '0');
    end if;
    end next_crc;

    function next_crc (
    crc : std_logic_vector;
    data : std_logic_vector;
    gen : std_logic_vector)
    return std_logic_vector is
    variable temp : std_logic_vector(crc'range);
    begin
    temp := crc;
    for i in data'left downto data'right loop
    temp := next_crc(temp, data(i), gen);
    end loop; -- i
    return temp;
    end next_crc;

    end crc_pack;


    Runar Gjelsvik wrote:
    > Hi,
    >
    > I tested the CRC tool at http://www.easics.be/webtools/crctool,
    > but I was wondering about the C variable.
    > Is this a variable containing the polynomial? Otherwise I don't understand
    > what sort bits it consist of....
    >
    >
    Ronald Hecht, May 12, 2004
    #7
  8. On Wed, 12 May 2004 12:32:09 +0200, Ronald Hecht
    <-rostock.de> wrote:

    >Recently we wrote a synthesizable CRC package. Feel free to add your
    >generator polys


    Would you consider adding this to opencores?

    http://www.opencores.org

    Regards,
    Allan.
    Allan Herriman, May 12, 2004
    #8
  9. Runar Gjelsvik

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    there is a VHDL code for crc here.. hope this helps..
    vhdlguru.blogspot.com/2010/03/vhdl-coding-method-for-cyclic.html
    vipinlal, Mar 8, 2010
    #9
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