create 400 clocks delay for a signal

[john]

Help wanted, thank you in advance;

I have two signals,
signal a: std_logic ;
signal b: std_logic ;

I try to delay "a " 400 clocks , then send to "b",
I use
a <= b after 400 clocks time;
I put the above code into my project, then download to the
FPGA(XC2v3000), the result is wrong,

then I use the "D" flip flop
signal a: std_logic ;
signal b: std_logic ;
signal temp1:std_logic ;
......
signal temp399:std_logic ;


delay : process (CLK)
if( CLK'event and CLK = '1' ) then
temp1<=a;
temp2<=temp1;
.......
b<=temp399;
end process;
then my project runs correctly on the FPGA chip,
I think there is a smart way to write(maybe use loop?)
temp1<=a;
temp2<=temp1;
.......
b<=temp399;
currently I use 400 lines in my code, I am novice in FPGA, I have no
idea how to simplify the code.
thanks

 

[Kai Harrekilde-Petersen]

Help wanted, thank you in advance;

I have two signals,
signal a: std_logic ;
signal b: std_logic ;

I try to delay "a " 400 clocks , then send to "b",
I use
a <= b after 400 clocks time;
I put the above code into my project, then download to the
FPGA(XC2v3000), the result is wrong,

And it should be - the "after <time>" construction is not synthesizable.
You need to write a state machine (400 stage pipeline comes to mind) to
create the 400 cycle delay.

signal delay_line : std_logic_vector[400 downto 1];

process(clk, rst)
begin
if reset = '0' then
delay_line <= (others => '0');
else if rising_edge(clk) then
b <= delay_line(400);
delay_line(400 downto 2) <= delay_line(399 downto 1);
delay_line(1) <= a
end if;
end process;


(major caveats with the syntax - it's been many moons since I last
wrote in VHDL)


Regards,


Kai