Creating a core from my VHDL code

Discussion in 'VHDL' started by axr0284, Jan 14, 2009.

  1. axr0284

    axr0284 Guest

    Hi,
    I wrote some code in VHDL and I would like to create a core targeting
    Xilinx Spartan-3E devices. I am clueless of how to proceed with that.
    1) I can synthesize the code using XST with an XCF timing constraint
    file which will create an NGC file. Is that considered a CORE?
    2) Will the NGC file contain the timing information from the XCF
    timing constraint file?
    3) Is there a way to actually area constrain it during synthesis?

    Thanks for the help,
    Amish
     
    axr0284, Jan 14, 2009
    #1
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