Creating a new Function

Discussion in 'VHDL' started by Eric, Dec 30, 2004.

  1. Eric

    Eric Guest

    With XST I'm unable to create my own function called "Erics_Gate". If I
    change the name to "and" or any other exsisting operator it works fine,
    but I'd like this function to be called "Erics_Gate".

    Any Ideas on how to define "Erics_Gate" as an operator?

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity mux is
    Port ( A, B : in STD_LOGIC;
    CLK : in STD_LOGIC;
    Y : out STD_LOGIC);
    end mux;

    architecture Behavioral of mux is

    function "Eric_gate" (L:std_ulogic; R:std_ulogic) return STD_ulogic is
    begin
    if L = '0' and R ='0' then return '1';
    elsif L = '0' and R ='1' then return '1';
    elsif L = '1' and R ='0' then return '0';
    else return '1';
    end if;
    end;
    begin

    Process
    begin
    wait until clk = '1';
    Y<= A Eric_gate B;

    end process;
    end Behavioral;
     
    Eric, Dec 30, 2004
    #1
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  2. Eric

    Jim Lewis Guest

    Eric,
    The only functions that can be called with infix notation
    are ones that are predefined by the language. For Erics_Gate,
    remove the "" in the definition and call it using function
    call notation:

    Y <= Erics_gate(A, B)

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    > With XST I'm unable to create my own function called "Erics_Gate". If I
    > change the name to "and" or any other exsisting operator it works fine,
    > but I'd like this function to be called "Erics_Gate".
    >
    > Any Ideas on how to define "Erics_Gate" as an operator?
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > use IEEE.NUMERIC_STD.ALL;
    >
    > entity mux is
    > Port ( A, B : in STD_LOGIC;
    > CLK : in STD_LOGIC;
    > Y : out STD_LOGIC);
    > end mux;
    >
    > architecture Behavioral of mux is
    >
    > function "Eric_gate" (L:std_ulogic; R:std_ulogic) return STD_ulogic is
    > begin
    > if L = '0' and R ='0' then return '1';
    > elsif L = '0' and R ='1' then return '1';
    > elsif L = '1' and R ='0' then return '0';
    > else return '1';
    > end if;
    > end;
    > begin
    >
    > Process
    > begin
    > wait until clk = '1';
    > Y<= A Eric_gate B;
    >
    > end process;
    > end Behavioral;
    >
     
    Jim Lewis, Dec 30, 2004
    #2
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  3. Eric

    Eric Guest

    Thanks this worked great!!!

    I also just got done reading your paper on "Coding a 40x40 Pipelined
    Multiplier". I really enjoyed this paper. I coded up every example; it
    was a good learning experiance for me. I hope to see more of your
    papers in the future.

    Thanks
    Eric
     
    Eric, Dec 30, 2004
    #3
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