Creating RAM in VHDL as Project

Discussion in 'VHDL' started by Avatar7, Apr 28, 2005.

  1. Avatar7

    Avatar7 Guest

    Hello !

    I am an IT-Student and work on a project creating entities in VHDL
    simulation RAMs. They shall function in diferant modes (EDO, FPM, SDRAM,
    DDR-RAM). The timing shall be smulated in two ways:
    Either the exact timing shall be simulated, second the real structure
    shall be simulated.
    My pleadge is now if I could be supportetd with some links or examplecode
    about how to ralize this problems

    Thanks in Advance
    Torben Rook
    Avatar7, Apr 28, 2005
    #1
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  2. Avatar7

    thomas Guest

    Avatar7 wrote:
    > Hello !
    >
    > I am an IT-Student and work on a project creating entities in VHDL
    > simulation RAMs. They shall function in diferant modes (EDO, FPM, SDRAM,
    > DDR-RAM). The timing shall be smulated in two ways:
    > Either the exact timing shall be simulated, second the real structure
    > shall be simulated.
    > My pleadge is now if I could be supportetd with some links or examplecode
    > about how to ralize this problems
    >
    > Thanks in Advance
    > Torben Rook
    >


    maybe you can find something here

    http://www.opencores.org/browse.cgi/by_category

    http://www.eda.org/fmf/wwwpages/Welcome.html

    --
    thomas
    thomas, Apr 28, 2005
    #2
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