Creating RAM in VHDL as Project

[Avatar7]

Hello !

I am an IT-Student and work on a project creating entities in VHDL
simulation RAMs. They shall function in diferant modes (EDO, FPM, SDRAM,
DDR-RAM). The timing shall be smulated in two ways:
Either the exact timing shall be simulated, second the real structure
shall be simulated.
My pleadge is now if I could be supportetd with some links or examplecode
about how to ralize this problems

Thanks in Advance
Torben Rook

 

[thomas]

Hello !

I am an IT-Student and work on a project creating entities in VHDL
simulation RAMs. They shall function in diferant modes (EDO, FPM, SDRAM,
DDR-RAM). The timing shall be smulated in two ways:
Either the exact timing shall be simulated, second the real structure
shall be simulated.
My pleadge is now if I could be supportetd with some links or examplecode
about how to ralize this problems

Thanks in Advance
Torben Rook

maybe you can find something here

http://www.opencores.org/browse.cgi/by_category

http://www.eda.org/fmf/wwwpages/Welcome.html