Creating Simulation Models

Discussion in 'VHDL' started by yy7d6@yahoo.com.ph, Jul 6, 2006.

  1. Guest

    i have found many IP Core packages having a 'VHDL Simulation model' and
    a 'Bitstream' but not having the synthesizable VHDL code,

    my question is how can i make a VHDL simulation model of my custom VHDL
    code just like that, because i will be porting it on a testbench.

    -yin
    , Jul 6, 2006
    #1
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  2. D Stanford Guest

    wrote:
    > i have found many IP Core packages having a 'VHDL Simulation model' and
    > a 'Bitstream' but not having the synthesizable VHDL code,
    >
    > my question is how can i make a VHDL simulation model of my custom VHDL
    > code just like that, because i will be porting it on a testbench.
    >
    > -yin


    IP CORESs don't have synthesizable code attached to them for a couple
    reasons. Maybe the code is too proprietary to give to you. Maybe the
    vendor doesn't trust the synthesizer to convert correctly for their
    FPGA.

    However, just because cores provide simulation only vhdl files, doesn't
    mean that it's necessary for you to do the same. If you have VHDL code,
    it is simulateable. The only reason I can think to make a simulation
    specific version of the code is if you'll get large speed increases on
    the simulation.

    Dave
    D Stanford, Jul 6, 2006
    #2
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