creating testbench template

V

Volker

hello,

I'm looking for template for creating a vhdl testbench. On
www.vhdl-online.de there was a testbench generator, but this application is
down :-(
I want to create a testbench-template according to my entity. Not creating
the real testbench only the formal template. I know the altera quartus
testbench template or the xilinx version. But I want to do the template
creating by my own to addapt for my coding syle.
Has anybody a skrip (like tcl or similar) to do the template according the
vhdl entity?

thanl for help
volker
 
V

Vince

Volker a écrit:
hello,

I'm looking for template for creating a vhdl testbench. On
www.vhdl-online.de there was a testbench generator, but this application is
down :-(
I want to create a testbench-template according to my entity. Not creating
the real testbench only the formal template. I know the altera quartus
testbench template or the xilinx version. But I want to do the template
creating by my own to addapt for my coding syle.
Has anybody a skrip (like tcl or similar) to do the template according the
vhdl entity?

You can edit your VHDL with XEmacs (and the vhdl-mode). In XEmacs there is a
copy/paste feature that allows you to copy an entity (or a component
declaration) to another entity, to a component declaration, to a component
instantiation, to a signal list and to a testbench.
 
M

Mike Treseler

Vince said:
You can edit your VHDL with XEmacs (and the vhdl-mode). In XEmacs there is a
copy/paste feature that allows you to copy an entity (or a component
declaration) to another entity, to a component declaration, to a component
instantiation, to a signal list and to a testbench.

vhdl-mode does this very well for emacs or xemacs.
It also supports templates to fill in the generic blanks.
Easiest way to try this is on a recent linux distribution.
Most have the latest vhdl-mode ready to go.

-- Mike Treseler
 

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