critical path

Discussion in 'VHDL' started by aimendj, Mar 18, 2009.

  1. aimendj

    aimendj

    Joined:
    Feb 12, 2009
    Messages:
    4
    Hello,

    i'm now implementing an entity wich compute the maximum of 4 signed inputs. the device target is Virtex 5. this implementation gives me 215 MHz of maximum frequency:

    ENTITY MAX4 IS
    GENERIC (CONSTANT M: natural := 5); -- input and output width
    Port (
    X1: in signed(M-1 downto 0);
    X2: in signed(M-1 downto 0);
    X3: in signed(M-1 downto 0);
    X4: in signed(M-1 downto 0);
    MAX: out signed(M-1 downto 0)); -- MAXIMUM Value
    end MAX4;

    ARCHITECTURE RTL OF MAX4 IS
    signal TEMP1: signed(M-1 downto 0);
    signal TEMP2: signed(M-1 downto 0);
    BEGIN
    -----------------------------------------------------------
    --
    -----------------------------------------------------------
    compare_x1:process(X1,X2)
    begin
    TEMP1 <= X1;
    if X1<X2 then
    TEMP1<=X2;
    end if;
    end process;
    compare_x3:process(X3,X4)
    begin
    TEMP2 <= X3;
    if X3<X4 then
    TEMP2<=X4;
    end if;
    end process;

    compare_temp:process(TEMP1,TEMP2)
    begin
    MAX_NXT<= TEMP1;
    if TEMP1<TEMP2 then
    MAX<=TEMP2;
    end if;
    end process;
    end;

    did any one have an idea how to implement the MAX4 function in better way to increase the frequency.

    Thanks,
    Aymen
     
    aimendj, Mar 18, 2009
    #1
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  2. aimendj

    aimendj

    Joined:
    Feb 12, 2009
    Messages:
    4
    by the way no pipelining is possible!!!!!!!!
     
    aimendj, Mar 18, 2009
    #2
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  3. aimendj

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    What is your clock speed? You already have a 'binary' search, so that will take two clock cycles. If Xilinx is taking more than two cycles (check the timing analysis) then you might be able to simplify the logic with some other syntax.

    How about this to do everything in one clock cycle:

    if (X1>X2) and (X1>X3) and (X1>X4) then Max <= X1;
    elsif
    (X2>X1) and (X2>X3) and (X2>X4) then Max <= X2;
    elsif
    (X3>X1) and (X3>X2) and (X3>X4) then Max <= X3;
    elsif
    (X4>X1) and (X4>X2) and (X4>X3) then Max <= X4;
    end if;
     
    JohnDuq, Mar 18, 2009
    #3
  4. aimendj

    aimendj

    Joined:
    Feb 12, 2009
    Messages:
    4
    what i implemented can be synthetized to 3 comparator and 3 multiplexer. but here u are implementing 12 comparator and 12 MUX or more.

    also u can't say that this circuit will work with 500Mhz it's the sunthetizer job to determin the max frequency.

    thanks for the help
     
    aimendj, Mar 19, 2009
    #4
  5. aimendj

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    You are correct. My techniques does takes more hardware. The trick is that it is not sequential; one process is not dependent upon another process to complete. That is where the time saving is possible (if the compiler is smart enough).

    When you want to optimize you really need to dig down to the root level and see what gates are being defined, and then go back to the top to figure out what it takes for faster logic to be implemented.

    Good luck
     
    JohnDuq, Mar 19, 2009
    #5
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