Cross clock domain control signal convey

Discussion in 'VHDL' started by legendbb, May 9, 2006.

  1. legendbb

    legendbb

    Joined:
    May 9, 2006
    Messages:
    1
    New comer thanks for help in advance,
    It's not about VHDL programming, but I didn't find electronics thread,

    Quartus II, Stratix II EP2S60

    Trying to use a 100MHz FSM to control a 400MHz module, some paths failed (either synchronous and asynchronous).

    400MHz module stands alone and leaves all external ports as pins, fmax fits well.

    Added FSM, use FSM output (wires) to send control to 400MHz module ports, problem.

    Solution could be simply to cut off register path (no tight timing requirement), buffer FSM outputs and let 400MHz to read them synchronously.

    Tried latche, DFF, no fruit.

    Wondering if there is any conventional solution for this kind of issue?

    Thanks again,
    legendbb, May 9, 2006
    #1
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