Cyclone III SFL Megafunction

Discussion in 'VHDL' started by Steffen Koepf, Jan 19, 2010.

  1. Hello,

    one more question ;-)
    i want to reprogram the configuration from a ATMega with
    it's ISP interface. Therefore i created a megafunction and
    routed the controlling signals out of the FPGA to the
    ATMega SPI Interface. Now there are nasty warnings from
    the fitter that i want to get rid of.

    Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
    Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
    Warning: Ignored reserve pin assignment to SPI programming pin DCLK
    Warning: Ignored reserve pin assignment to SPI programming pin Data[0]

    Is a reserve pin assignment the default assignment of all pins not
    directly assigned a value? What to do here?

    Next:

    Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment
    Warnings report for details

    In the I/O Assignment Warnings it complains that the driving strength is
    not specified of megafunction internal signals like
    sfl:U16|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0
    But copying this signal in the assignment editor and assigning a current
    drive strength seems to have no effect.

    Thanks in advance,

    Steffen
     
    Steffen Koepf, Jan 19, 2010
    #1
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  2. On 1/19/2010 4:27 PM, Steffen Koepf wrote:
    > Hello,
    >
    > one more question ;-)
    > i want to reprogram the configuration from a ATMega with
    > it's ISP interface. Therefore i created a megafunction and
    > routed the controlling signals out of the FPGA to the
    > ATMega SPI Interface. Now there are nasty warnings from
    > the fitter that i want to get rid of.
    >
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
    > Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
    > Warning: Ignored reserve pin assignment to SPI programming pin DCLK
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[0]
    >
    > Is a reserve pin assignment the default assignment of all pins not
    > directly assigned a value? What to do here?


    You need to allow these pins to be used as general-purpose I/O. By
    default, Quartus reserves these pins and does not let you assign signals
    to them. Go to:

    Assignments -> Settings -> Device -> Device and Pin Options ->
    Dual-Purpose Pins

    ....select the pins you need to assign signals to, and change their
    setting to "Use as regular I/O"

    --
    Charles Steinkuehler
     
    Charles Steinkuehler, Feb 2, 2010
    #2
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  3. On 1/19/2010 4:27 PM, Steffen Koepf wrote:
    > Hello,
    >
    > one more question ;-)
    > i want to reprogram the configuration from a ATMega with
    > it's ISP interface. Therefore i created a megafunction and
    > routed the controlling signals out of the FPGA to the
    > ATMega SPI Interface. Now there are nasty warnings from
    > the fitter that i want to get rid of.
    >
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
    > Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
    > Warning: Ignored reserve pin assignment to SPI programming pin DCLK
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[0]
    >
    > Is a reserve pin assignment the default assignment of all pins not
    > directly assigned a value? What to do here?


    You need to allow these pins to be used as general-purpose I/O. By
    default, Quartus reserves these pins and does not let you assign signals
    to them. Go to:

    Assignments -> Settings -> Device -> Device and Pin Options ->
    Dual-Purpose Pins

    ....select the pins you need to assign signals to, and change their
    setting to "Use as regular I/O"

    --
    Charles Steinkuehler
     
    Charles Steinkuehler, Feb 2, 2010
    #3
  4. On Jan 19, 4:27 pm, Steffen Koepf <> wrote:
    > Hello,
    >
    > one more question ;-)
    > i want to reprogram the configuration from a ATMega with
    > it's ISP interface. Therefore i created a megafunction and
    > routed the controlling signals out of the FPGA to the
    > ATMega SPI Interface. Now there are nasty warnings from
    > the fitter that i want to get rid of.
    >
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
    > Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
    > Warning: Ignored reserve pin assignment to SPI programming pin DCLK
    > Warning: Ignored reserve pin assignment to SPI programming pin Data[0]
    >
    > Is a reserve pin assignment the default assignment of all pins not
    > directly assigned a value? What to do here?


    You need to allow these pins to be used as general-purpose I/O. By
    default, Quartus reserves these pins and does not let you assign
    signals to them. Go to:

    Assignments -> Settings -> Device -> Device and Pin Options ->
    Dual-Purpose Pins

    ....select the pins you need to assign signals to, and change their
    setting to "Use as regular I/O"

    --
    Charles Steinkuehler
     
    Charles Steinkuehler, Feb 2, 2010
    #4
    1. Advertising

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