D flip flop setup and hold timings.

Joined
Jun 3, 2010
Messages
1
Reaction score
0
Hello everyone,
I am new to this Website and as well as VHDL??

i have got exams soon and need to work out few problems in vhdl, hope you guys help me quickly...

problem 1)

how do i make vhdl code for asynchronous reset D flip flop by including setup (SUT) and hold (HT) violations ? ? ? ?

Please help me guys on this..appreciated !!
:wink:
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Similar Threads

2 flip-flop synchronizer 1
State machine with D Flip Flop 6
D-Flip-flop 3
D FLIP-FLOP 6
SR Flip Flop 16
2 JK Circuit in VHDL 0
Setup and Hold Times 1
Rising Edge D flip Flop code in c++ 2

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,484
Members
44,903
Latest member
orderPeak8CBDGummies

Latest Threads

Top