D flip flop setup and hold timings.

Discussion in 'VHDL' started by luvdhams23, Jun 3, 2010.

  1. luvdhams23

    luvdhams23

    Joined:
    Jun 3, 2010
    Messages:
    1
    Hello everyone,
    I am new to this Website and as well as VHDL??

    i have got exams soon and need to work out few problems in vhdl, hope you guys help me quickly...

    problem 1)

    how do i make vhdl code for asynchronous reset D flip flop by including setup (SUT) and hold (HT) violations ? ? ? ?

    Please help me guys on this..appreciated !!
    :wink:
     
    luvdhams23, Jun 3, 2010
    #1
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