D FLIP-FLOP

Discussion in 'VHDL' started by ABS, Dec 15, 2005.

  1. ABS

    ABS Guest

    hiii
    i need immeadite help...
    i have to deliver a presentation. suppose i have to verify a D flip
    flop, what are the verification stages, how will i proceed with it.
    what are the steps to begin till end. its important so can any one out
    here just brief it out to me.

    thanks a million.

    bye
     
    ABS, Dec 15, 2005
    #1
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  2. HI,

    ABS wrote::
    > i need immeadite help...
    > i have to deliver a presentation. suppose i have to verify a D flip
    > flop, what are the verification stages, how will i proceed with it.
    > what are the steps to begin till end. its important so can any one out
    > here just brief it out to me.


    There's a lack of information in your request.

    - Who has to be impressed by this representation
    - On which level do you need to verify?
    - Against which scenario do you have to verify?
    - What D-FF exactly?
    - How much will you pay?

    Step one: collect all necessary requirements for your task
    Further steps may be easy after step one.

    bye Thomas
     
    Thomas Stanka, Dec 15, 2005
    #2
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  3. ABS

    ABS Guest

    hey..

    this is a presentation that has to be delivered to my team,to teh
    members of my team itself. what if in case they ask, explain with an
    example, say u givn a D Flip Flop to verify, how will u proceed. what
    do u plan n how u cary on with the verification. What m i suppose to
    say. how will i proceed. can u plzzzzz tell me in brief..!!

    thanks
     
    ABS, Dec 15, 2005
    #3
  4. ABS

    Guest

    I assume you know how a D flip flop works. If you don't, you need to
    find out before you start. From the definition of a D flip flop you
    will know what its expected behaviour is given certain inputs. You
    simply need to supply the inputs and verify that the flip flop responds
    according to its definition.

    Charles
     
    , Dec 15, 2005
    #4
  5. ABS

    Niv Guest

    For a deep verification, you can monitor the outputs and then verify
    that
    for the given outputs (and transitions) the correct stimulii were
    received,
    i.e. no false switching as well as correct behaviour for usual inputs.
    This does mean firing a whole load of different vectors at the inputs,
    using
    all possible combinations of multi valued logic 0, 1, Z, and maybe X.

    Just an idea.

    Kev P.
     
    Niv, Dec 15, 2005
    #5
  6. ABS

    David Binnie Guest

    D _______________|¬¬¬¬¬¬¬¬¬|______________|¬¬¬¬¬¬¬¬¬¬¬¬|__________

    Clock _____|¬¬¬¬|____|¬¬¬¬|____|¬¬¬¬|____|¬¬¬¬|____|¬¬¬¬|____|¬¬¬¬|____

    Reset __________________|¬¬¬¬¬¬¬¬¬¬¬¬¬|______________________

    Q ???????????????????????????????????????????????????????????????????


    "ABS" <> wrote in message
    news:...
    > hiii
    > i need immeadite help...
    > i have to deliver a presentation. suppose i have to verify a D flip
    > flop, what are the verification stages, how will i proceed with it.
    > what are the steps to begin till end. its important so can any one out
    > here just brief it out to me.
    >
    > thanks a million.
    >
    > bye
    >
     
    David Binnie, Dec 15, 2005
    #6
  7. ABS

    ABS Guest

    thanks to my query...
    appreciated...
     
    ABS, Dec 16, 2005
    #7
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