Data conversion

Discussion in 'VHDL' started by iliya24, May 6, 2012.

  1. iliya24

    iliya24

    Joined:
    May 6, 2012
    Messages:
    1
    Hello.

    I am a new to vhdl and i using a cypress software.

    In my project i need to convert integer to std_logic vector i did some research and found

    this functions :v1 <= conv_std_logic_vector(u1, 4); i added a std_logic_arith package but

    when i run compile it gives me error that :undeclared name: conv_std_logic_vector.

    Than i tried to do it like this i2bv(i; w) converts integer i to binary equivalent and expresses as a bit_vector of length
    w.
    Usage:
    variable i: integer range 0 to 31;
    signal a: bit_vector(0 to 4);
    a <= i2bv(i, 5);

    this i found at wrap reference.

    still got tha same error that i2bv is t :undeclared name.

    I added a int_math and bv_math like use work.bv_math.all; and use work.int_math.all;
    but i got error that wrap can;t find those packages .

    My question were i did wrong and how to convert?

    Thx.
     
    iliya24, May 6, 2012
    #1
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