Data flow, change with the time

[piolin86]

Hello, I thinks that my problem is easy but I dont know the answer, I only want a program with 3 output send different vector in different time. If I try to cpy the port in a signal quartus say me impossible two values. So I try to make wiht different architecture but only copy the last, could you help me?

ENTITY prueba IS
port
(
a,b,c ut std_logic_vector (0 TO 6) );
END prueba;
ARCHITECTURE test_nand OF prueba IS
SIGNAL a_test, b_test, c_test : std_logic_vector (0 TO 6);
BEGIN
a <= "0000000" after 0 ns;
b<="0000000" after 0 ns;
c<= "0000000" after 0 ns;
END test_nand;

ARCHITECTURE test_nand2 OF prueba IS
BEGIN
a <="1010111" after 20 ns;
b<="0000001" after 0 ns;
c<= "0000100" after 0 ns;
END test_nand2;

ARCHITECTURE test_nand3 OF prueba IS
BEGIN
a <="0000000" after 30 ns;
b<="0000000" after 10 ns;
c<= "0000000" after 15 ns;
END test_nand3;

Thanks

 

[piolin86]

is it easy?

 

[jeppe]

Yes it is - like this.

a <= "00001111" after 0 ns, "11101010" after 20 ns, "10101010" after 50 ns;

Search the net for the free interactive book: EVITA VHDL
Chapter 7.4.2 got an example

Your welcome

 

[piolin86]

Thanks so much

 

[piolin86]

Only one question more, I dont know how it sould be the entity and the architeture, something like this:

entity BancoPruebas is port(
data1, data2, data3: out std_logic_vector (0 TO 3);
clk, reset: IN std_logic);
end BancoPruebas;

architecture a of BancoPruebas is
begin
TEMPO: process (clk, reset)
Begin
If reset = '1' THEN
data1<= "0000" ;
Elsif (clk'event AND clk ='1') THEN
data1<= "0101" After 50ns;
data1<= "0000" After 100ns;

end if ;
END PROCESS tempo;

end a;

 

[jeppe]

Your not allowed to mix:

Process( Clk) ... Clk'event

and

Data1 <= .... after ... ns;

 

[piolin86]

sorry?? i dont understan you

 

[piolin86]

like this
entity BancoPruebas is port(
data1, data2, data3: out std_logic_vector (0 TO 3);
clk, reset: IN std_logic);
end BancoPruebas;

architecture a of BancoPruebas is
signal AM: std_logic_vector (0 TO 3);
begin
TEMPO: process (clk, reset)
Begin

Am <= "0010" after 100 ns,
"1100" after 240 ns,
"1010" after 350 ns;
data1 <=Am;


END PROCESS tempo;

 

[jeppe]

entity BancoPruebas is port(
data1, data2, data3: out std_logic_vector (0 TO 3);
clk, reset: IN std_logic);
end BancoPruebas;

architecture a of BancoPruebas is
signal AM: std_logic_vector (0 TO 3);
begin

-- This code will ONLY be useful for simulation
TEMPO: process
Begin
     wait for 100 ns;
     Am <= "0010" ;  -- after 100 ns,
     data1 <=Am;
     wait for 140 ns;
     Am <= "1100";  -- after 240 ns,
     data1 <=Am;
     wait for 110 ns;
     Am  <= "1010";  -- after 350 ns;
     data1 <=Am;
     wait;  -- for ever
END PROCESS tempo;