Data flow, change with the time

Discussion in 'VHDL' started by piolin86, Oct 19, 2011.

  1. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
    7
    Hello, I thinks that my problem is easy but I dont know the answer, I only want a program with 3 output send different vector in different time. If I try to cpy the port in a signal quartus say me impossible two values. So I try to make wiht different architecture but only copy the last, could you help me?

    ENTITY prueba IS
    port
    (
    a,b,c :eek:ut std_logic_vector (0 TO 6) );
    END prueba;
    ARCHITECTURE test_nand OF prueba IS
    SIGNAL a_test, b_test, c_test : std_logic_vector (0 TO 6);
    BEGIN
    a <= "0000000" after 0 ns;
    b<="0000000" after 0 ns;
    c<= "0000000" after 0 ns;
    END test_nand;

    ARCHITECTURE test_nand2 OF prueba IS
    BEGIN
    a <="1010111" after 20 ns;
    b<="0000001" after 0 ns;
    c<= "0000100" after 0 ns;
    END test_nand2;

    ARCHITECTURE test_nand3 OF prueba IS
    BEGIN
    a <="0000000" after 30 ns;
    b<="0000000" after 10 ns;
    c<= "0000000" after 15 ns;
    END test_nand3;

    Thanks
    piolin86, Oct 19, 2011
    #1
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  2. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
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    is it easy?
    piolin86, Oct 19, 2011
    #2
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  3. piolin86

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Yes it is - like this.

    a <= "00001111" after 0 ns, "11101010" after 20 ns, "10101010" after 50 ns;

    Search the net for the free interactive book: EVITA VHDL
    Chapter 7.4.2 got an example

    Your welcome
    jeppe, Oct 21, 2011
    #3
  4. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
    7
    Thanks so much
    piolin86, Nov 3, 2011
    #4
  5. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
    7
    Only one question more, I dont know how it sould be the entity and the architeture, something like this:

    entity BancoPruebas is port(
    data1, data2, data3: out std_logic_vector (0 TO 3);
    clk, reset: IN std_logic);
    end BancoPruebas;

    architecture a of BancoPruebas is
    begin
    TEMPO: process (clk, reset)
    Begin
    If reset = '1' THEN
    data1<= "0000" ;
    Elsif (clk'event AND clk ='1') THEN
    data1<= "0101" After 50ns;
    data1<= "0000" After 100ns;

    end if ;
    END PROCESS tempo;

    end a;
    piolin86, Nov 3, 2011
    #5
  6. piolin86

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Your not allowed to mix:

    Process( Clk) ... Clk'event

    and

    Data1 <= .... after ... ns;
    jeppe, Nov 4, 2011
    #6
  7. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
    7
    sorry?? i dont understan you :(
    piolin86, Nov 5, 2011
    #7
  8. piolin86

    piolin86

    Joined:
    Oct 13, 2011
    Messages:
    7
    like this
    entity BancoPruebas is port(
    data1, data2, data3: out std_logic_vector (0 TO 3);
    clk, reset: IN std_logic);
    end BancoPruebas;

    architecture a of BancoPruebas is
    signal AM: std_logic_vector (0 TO 3);
    begin
    TEMPO: process (clk, reset)
    Begin

    Am <= "0010" after 100 ns,
    "1100" after 240 ns,
    "1010" after 350 ns;
    data1 <=Am;


    END PROCESS tempo;
    piolin86, Nov 6, 2011
    #8
  9. piolin86

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Code:
    entity BancoPruebas is port(
    data1, data2, data3: out std_logic_vector (0 TO 3);
    clk, reset: IN std_logic);
    end BancoPruebas;
    
    architecture a of BancoPruebas is
    signal AM: std_logic_vector (0 TO 3);
    begin
    
    -- This code will ONLY be useful for simulation
    TEMPO: process
    Begin
         wait for 100 ns;
         Am <= "0010" ;  -- after 100 ns,
         data1 <=Am;
         wait for 140 ns;
         Am <= "1100";  -- after 240 ns,
         data1 <=Am;
         wait for 110 ns;
         Am  <= "1010";  -- after 350 ns;
         data1 <=Am;
         wait;  -- for ever
    END PROCESS tempo;
    jeppe, Nov 12, 2011
    #9
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