Data Register Block

Discussion in 'VHDL' started by Ukanbal, Mar 7, 2009.

  1. Ukanbal

    Ukanbal

    Joined:
    Mar 7, 2009
    Messages:
    9
    Hi;

    for my next assignment i am supposed to build the data path of a 32 bit processor which uses 8 x 32 bit registers as a DRB. i have managed to finish up every component but this DRB. as any other DRB this one uses 3 address inputs wAdd1 (write address), rAdd1 and rAdd2 (the 2 register addresses), uses a wen_rf for write enable, clr_rf to clear all the registers inside the block, uses a 32 bit wData input and has 2 output data signals both 32 bit rData1 and rData2.
    And for the assignment we have to implement the 8 registers inside the DRB as well. Here is my code
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY Reg8 IS
    PORT(
    clr_RF : IN std_logic;
    wen_RF : IN std_logic;
    wAdd1 : IN STD_LOGIC_VECTOR(2 downto 0);
    rAdd1 : IN STD_LOGIC_VECTOR(2 downto 0);
    rAdd2 : IN STD_LOGIC_VECTOR(2 downto 0);
    wdata : IN STD_LOGIC_VECTOR(31 downto 0);
    rData1 : OUT STD_LOGIC_VECTOR(31 downto 0);
    rData2 : OUT STD_LOGIC_VECTOR(31 downto 0);
    r0,r1,r2,r3 : BUFFER STD_LOGIC_VECTOR(31 downto 0);
    r4,r5,r6,r7 : BUFFER STD_LOGIC_VECTOR(31 downto 0);
    clk : IN std_logic);
    END Reg8;

    ARCHITECTURE desc OF Reg8 IS

    BEGIN
    Process( wen_RF, clr_RF, wdata, clk, wAdd1, rAdd1, rAdd2)
    BEGIN
    IF( clr_RF = '1') THEN
    r0 <= (OTHERS => '0');
    r1 <= (OTHERS => '0');
    r2 <= (OTHERS => '0');
    r3 <= (OTHERS => '0');
    r4 <= (OTHERS => '0');
    r5 <= (OTHERS => '0');
    r6 <= (OTHERS => '0');
    r7 <= (OTHERS => '0');
    END IF;

    CASE rAdd1 IS
    WHEN "000" =>
    rData1 <= r0;
    WHEN "001" =>
    rData1 <= r1;
    WHEN "010" =>
    rData1 <= r2;
    WHEN "011" =>
    rData1 <= r3;
    WHEN "100" =>
    rData1 <= r4;
    WHEN "101" =>
    rData1 <= r5;
    WHEN "110" =>
    rData1 <= r6;
    WHEN "111" =>
    rData1 <= r7;
    END CASE;

    CASE rAdd2 IS
    WHEN "000" =>
    rData2 <= r0;
    WHEN "001" =>
    rData2 <= r1;
    WHEN "010" =>
    rData2 <= r2;
    WHEN "011" =>
    rData2 <= r3;
    WHEN "100" =>
    rData2 <= r4;
    WHEN "101" =>
    rData2 <= r5;
    WHEN "110" =>
    rData2 <= r6;
    WHEN "111" =>
    rData2 <= r7;
    END CASE;

    IF( clk'EVENT) AND (clk = '1') THEN
    IF ( wen_RF = '1') THEN
    IF ( wAdd1 = "000") THEN
    r0 <= wdata;
    r1 <= r1;
    r2 <= r2;
    r3 <= r3;
    r4 <= r4;
    r5 <= r5;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "001") THEN
    r0 <= r0;
    r1 <= wdata;
    r2 <= r2;
    r3 <= r3;
    r4 <= r4;
    r5 <= r5;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "010") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= wdata;
    r3 <= r3;
    r4 <= r4;
    r5 <= r5;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "011") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= r2;
    r3 <= wdata;
    r4 <= r4;
    r5 <= r5;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "100") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= r2;
    r3 <= r3;
    r4 <= wdata;
    r5 <= r5;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "101") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= r2;
    r3 <= r3;
    r4 <= r4;
    r5 <= wdata;
    r6 <= r6;
    r7 <= r7;
    ELSIF ( wAdd1 = "110") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= r2;
    r3 <= r3;
    r4 <= r4;
    r5 <= r5;
    r6 <= wdata;
    r7 <= r7;
    ELSIF ( wAdd1 = "111") THEN
    r0 <= r0;
    r1 <= r1;
    r2 <= r2;
    r3 <= r3;
    r4 <= r4;
    r5 <= r5;
    r6 <= r6;
    r7 <= wdata;
    END IF;
    END IF;
    END IF;

    END PROCESS;
    END desc;



    i have a problem with the 8 registers inside. they do not hold their data outside the clock therefore not allowing me to use this code. how can i fix this problem or is there another way to implement those 8 registers inside?
    Thanks a lot
     
    Last edited: Mar 7, 2009
    Ukanbal, Mar 7, 2009
    #1
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