Data type used in VHDL

Discussion in 'VHDL' started by ecenus, Sep 22, 2008.

  1. ecenus

    ecenus

    Joined:
    Sep 22, 2008
    Messages:
    4
    Hi,

    I am newbie to VHDL design. I came across a question of using VHDL.

    I'd like to output a 17 bit data through one port (one pin in an Altera chip) to my DSP on the the same circuit board. Each bit, either 0 or 1, stands for an error detected in my circuit. Say, if the second bit turns to 1, I will know something is wrong with my temperature sensor....

    But, when I set the port as STD_LOGIC_VECTOR (0 To 16), I got the error message that I can not send such data through one pin but 17 pins....

    Now, I want to know if I want to send my 17-bit data through one port. What data type should I use?

    Your help is highly appreciated!

    :loo:
     
    ecenus, Sep 22, 2008
    #1
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  2. ecenus

    Steff

    Joined:
    Sep 8, 2008
    Messages:
    11
    Hi,

    if a one stays for an error, you can do this:

    PHP:
    library ieee;
      use 
    ieee.std_logic_1164.all;
      use 
    ieee.std_logic_misc.or_reduce;

    signal s_error_vec  std_logic_vector(0 to 16);
    signal s_error_flag std_logic;

    begin

      s_error_flag 
    <= or_reduce(s_error_vec);  

    Did you means this?

    Bye, Steff
     
    Last edited: Sep 22, 2008
    Steff, Sep 22, 2008
    #2
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  3. ecenus

    ecenus

    Joined:
    Sep 22, 2008
    Messages:
    4
    Hi, Steff,

    Thank you for your reply.

    Maybe I did not indicate it clearly in my last post. I actually set the code like this:

    ................
    data_out: OUT STD_LOGIC_VECTOR (0 TO 16));

    CASE fault_count IS
    WHEN 0 => data_out(0) <= flt1;
    WHEN 1 => data_out(1) <= flt2;
    WHEN 2 => data_out(2) <= flt3;
    WHEN 3 => data_out(3) <= flt4;
    WHEN 4 => data_out(4) <= flt5;
    WHEN 5 => data_out(5) <= flt6;
    WHEN 6 => data_out(6) <= flt7;
    WHEN 7 => data_out(7) <= flt8;
    WHEN 8 => data_out(8) <= flt9;
    WHEN 9 => data_out(9) <= flt10;
    WHEN 10 => data_out(10) <= flt11;
    WHEN 11 => data_out(11) <= flt12;
    WHEN 12 => data_out(12) <= flt13;
    WHEN 13 => data_out(13) <= flt14;
    WHEN 14 => data_out(14) <= flt15;
    WHEN 15 => data_out(15) <= flt16;
    WHEN 16 => data_out(16) <= flt17;
    WHEN OTHERS => NULL;
    END CASE;

    But, I set "data_out" at PIN_K20, which is just one pin. but I was told the system requires 17 pins. I think I made a mistake here. Do you know what data type I should set "data_out" and set each bit standing for one error bit required in my design?

    Thanks, again!

    -ecenus
     
    ecenus, Sep 22, 2008
    #3
  4. ecenus

    Steff

    Joined:
    Sep 8, 2008
    Messages:
    11
    Hi ecenus,

    std_logic_vector is the right type for your design.

    If you want to transmit this vector you have two different approaches:

    1. sequentiell design:
    You have one pin and you have to send your data bit by bit. 5 clocks would be enough. (1 bit of the error message/clock cycle)

    2. parallel design:
    You have more than one pin. Then you can transmit your data in parallel. 5 pins would be enough. (1 error message/ clock cycle)

    If its enough only to see whether an error was occured then you can take the method I told you already at the last post.

    At present I have no further ideas.

    Steff
     
    Last edited: Sep 23, 2008
    Steff, Sep 23, 2008
    #4
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