data types and arithmetic ops

[mkr]

I am new to VHDL and in my first project i am using std_logic_vector,
unsigned and integer types with type conversions between them. This is
required as std_logic_vector is not allowing "+" operator on them.

Why doesn't VHDL allow arithmetic operations on std_logic_vector?
Why automatic type conversions are not done on these types?
Are all these types synthesizable?
Also want to know the difference in the hardware produced with each of
these types.

Appreciate if someone explains. Thanks in advance.

 

[KJ]

I am new to VHDL and in my first project i am  using std_logic_vector,
unsigned and integer types with type conversions between them. This is
required as std_logic_vector is not allowing "+" operator on them.

Why doesn't VHDL allow arithmetic operations on std_logic_vector?

Because a std_logic_vector is simply a collection of bits, there isn't
any implied numeric interpretation.

Why automatic type conversions are not done on these types?

Should "FF" be interpreted as...
1. "255" (i.e. an unsigned integer)
2. "-1" (i.e. a signed integer)

Whichever answer you choose, others will disagree.

Are all these types synthesizable?

Yes and the type conversion use no logic resources either. They
simply tell the synthesis tool how you would like to interpret the
vector. Ambiguity as is demonstrated in the above is not a 'good'
thing.

Also want to know the difference in the hardware produced with each of
these types.

Differences in hardware when doing what? When resizing an unsigned to
make it bigger (as an example), zeros will be padded on to the left.
When resizing a signed it will pad with the current leftmost bit which
is the sign bit.

KJ

 

[mkr]

Because a std_logic_vector is simply a collection of bits, there isn't
any implied numeric interpretation.


Should "FF" be interpreted as...
1. "255" (i.e. an unsigned integer)
2. "-1" (i.e. a signed integer)

Whichever answer you choose, others will disagree.


Yes and the type conversion use no logic resources either.  They
simply tell the synthesis tool how you would like to interpret the
vector.  Ambiguity as is demonstrated in the above is not a 'good'
thing.


Differences in hardware when doing what?  When resizing an unsigned to
make it bigger (as an example), zeros will be padded on to the left.
When resizing a signed it will pad with the current leftmost bit which
is the sign bit.

KJ

Thanks, KJ. Not when resizing; If I have these three types declared
in my design and are of same size, will there be any difference in
logic produced or resources used?

m

 

[Tricky]

Thanks, KJ. Not when resizing; If I have these three types declared
in  my design and are of same size, will there be any difference in
logic produced or resources used?

m

No, the logic used is identical when adding/subtracting/multiplying/
equals two signed numbers uses exactly the same logic as two unsigned
numbers. The synthesiser and hardware just see a collection of bits.
The unsigned and signed types are mostly there for user clarification
(other than when resizing a vector, when the extra bits makes life
important).

There is a difference when doing comparisons other than equals, but
the amount of logic is the same, the change is in how it's implemented.

 

[beky4kr]

No, the logic used is identical when adding/subtracting/multiplying/
equals two signed numbers uses exactly the same logic as two unsigned
numbers. The synthesiser and hardware just see a collection of bits.
The unsigned and signed types are mostly there for user clarification
(other than when resizing a vector, when the extra bits makes life
important).

There is a difference when doing comparisons other than equals, but
the amount of logic is the same, the change is in how it's implemented.

You may want to see some examples from ESA leon processor project.
I add some functionality and you can download it from ny site.
http://bknpk.no-ip.biz/LEON/pk_i2c_slave_model.vhd

 

[pankaj.goel]

>I am new to VHDL and in my first project i am using std_logic_vector,
>unsigned and integer types with type conversions between them. This is
>required as std_logic_vector is not allowing "+" operator on them.

>Why doesn't VHDL allow arithmetic operations on std_logic_vector?


Hi Friends,
To solve the above problem, make sure following library files are added in your design:
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------
Now, arithmetic operator + will work with std_logic_vector types.

regards
pankaj