DCM Core cannot generate output

Discussion in 'VHDL' started by uche, Apr 15, 2010.

  1. uche

    uche Guest

    Hello All,

    I have instantiated a DCM core with an input frequency of 32 MHz clock
    signal from the device. I would like to recieve a 96 MHz output signal
    from the DCM core, so I set the .xwa file to multiply the incomming
    signal by 3. When I generate the bit stream and run the design on my
    board, the FX pin doesn't seem to produce a frequency. I know I am
    doing something incorrectly here, do I have to reset the DCM core, or
    use another signal from the DCM core to obtain my desired output or
    whatever ... please help.

    Thanks,
     
    uche, Apr 15, 2010
    #1
    1. Advertising

  2. uche

    d_s_klein Guest

    On Apr 15, 1:28 pm, uche <> wrote:
    > Hello All,
    >
    > I have instantiated a DCM core with an input frequency of 32 MHz clock
    > signal from the device. I would like to recieve a 96 MHz output signal
    > from the DCM core, so I set the .xwa file to multiply the incomming
    > signal by 3. When I generate the bit stream and run the design on my
    > board, the FX pin doesn't seem to produce a frequency. I know I am
    > doing something incorrectly here, do I have to reset the DCM core, or
    > use another signal from the DCM core to obtain my desired output or
    > whatever ... please help.
    >
    > Thanks,


    Step one: Post to proper group (eg comp.arch.fpga)

    When you post there, include the chip type you're trying to put a DCM
    into.

    If this is your "first time ever" working with DCM's, you might make
    more progress working in schematic mode rather than HDL mode. Might.

    RK
     
    d_s_klein, Apr 16, 2010
    #2
    1. Advertising

  3. uche

    naliali Guest

    What is the FPGA you are using?
    How do you know FX clock doesn't work? you can check it by a simple
    counter running at ClkFX domain, and comparing it by another counter
    running at Clk0 domain(offcourse if you have an interface to read the
    results!). does Clk0 output of DCM works properly?
    if yes then the following facts may cause this problem.
    in the FPGAs the input signal to DCM must be greater than an specific
    frequency unless the internal DLL can't lock. it depends on the
    generation of FPGA you are using, for wxample in virtex-4 devices the
    minimum input frequency is 32 M. Also there is an attribute for
    setting working mode of internal DLL of DCM, named
    "DLL_FREQUENCY_MODE", setting it "High" or "Low" changes the
    limitation for input and output frequencies. if DCM sets to work on
    LOW mode and FX clock becomes more than maximum allowable frequency in
    the LOW mode, FX will not work. chek these parameters for your device.

    good luck
    Ali Noroozi
     
    naliali, Apr 20, 2010
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Replies:
    1
    Views:
    1,319
    Marco
    Jan 3, 2006
  2. prakash

    Xilinx-DCM Timing warning

    prakash, Apr 10, 2006, in forum: VHDL
    Replies:
    0
    Views:
    3,571
    prakash
    Apr 10, 2006
  3. zlotawy

    dcm error

    zlotawy, Jun 9, 2007, in forum: VHDL
    Replies:
    2
    Views:
    916
    zlotawy
    Jun 9, 2007
  4. TheThunder

    DCM clock signal output

    TheThunder, Jun 11, 2007, in forum: VHDL
    Replies:
    1
    Views:
    670
    Andy Peters
    Jun 12, 2007
  5. Pieter
    Replies:
    3
    Views:
    1,121
Loading...

Share This Page