DDR Why not

Discussion in 'VHDL' started by nfirtaps, Mar 14, 2007.

  1. nfirtaps

    nfirtaps Guest

    I am in the unfortunate situation of not having access to a PLL on my
    Altera and need to deserialize a DDR signal. It would be most
    advantageous to double the clock rate and sample on every rising edge
    to deserialze my DDR signal. I have read on this forum there are some
    circuits that do not require a PLL to double the clock (using some
    xors, nots and ff's), and I have implemented these circuits. They
    seem to be junk, and are very frequency dependant.

    I have also read that you cannot take the clock, the inverted clock
    and deserialize using rising egde flip flops to sample the signal?
    Why is this?

    Thanks,
    Lloyd
    nfirtaps, Mar 14, 2007
    #1
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  2. nfirtaps

    KJ Guest

    On Mar 14, 11:59 am, "nfirtaps" <> wrote:
    > I am in the unfortunate situation of not having access to a PLL on my
    > Altera and need to deserialize a DDR signal. It would be most
    > advantageous to double the clock rate and sample on every rising edge
    > to deserialze my DDR signal. I have read on this forum there are some
    > circuits that do not require a PLL to double the clock (using some
    > xors, nots and ff's), and I have implemented these circuits. They
    > seem to be junk, and are very frequency dependant.

    Just curious, in what way are they 'junk'?

    >
    > I have also read that you cannot take the clock, the inverted clock
    > and deserialize using rising egde flip flops to sample the signal?
    > Why is this?
    >

    Usually it's because the duty cycle is not very well controlled by the
    time it gets to the point where you need it so your 'falling' edge
    doesn't occur anywhere near the midpoint of the clock cycle. Then
    about all you can do is play games with resistors and capacitors to
    try to tweak the edges to be just right....it's not a robust solution.

    Even without a PLL you can easily make a divider though to generate a
    clock enable. If you can, change the oscillator to 2x of what you
    have now and use that as your clock instead throughout the design.
    Use the output of the divider as the clock enable for anything that
    needs to run at the 1x speed.

    Kevin Jennings
    KJ, Mar 14, 2007
    #2
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  3. nfirtaps

    nfirtaps Guest

    On Mar 14, 10:22 am, "KJ" <> wrote:
    > On Mar 14, 11:59 am, "nfirtaps" <> wrote:> I am in the unfortunate situation of not having access to a PLL on my
    > > Altera and need to deserialize a DDR signal. It would be most
    > > advantageous to double the clock rate and sample on every rising edge
    > > to deserialze my DDR signal. I have read on this forum there are some
    > > circuits that do not require a PLL to double the clock (using some
    > > xors, nots and ff's), and I have implemented these circuits. They
    > > seem to be junk, and are very frequency dependant.

    >
    > Just curious, in what way are they 'junk'?
    >


    When you look on the output on the scope it looks horrible. The
    waveform is very distored, and it is very dependant on frequency.

    >
    >
    > > I have also read that you cannot take the clock, the inverted clock
    > > and deserialize using rising egde flip flops to sample the signal?
    > > Why is this?

    >
    > Usually it's because the duty cycle is not very well controlled by the
    > time it gets to the point where you need it so your 'falling' edge
    > doesn't occur anywhere near the midpoint of the clock cycle. Then
    > about all you can do is play games with resistors and capacitors to
    > try to tweak the edges to be just right....it's not a robust solution.
    >


    Looks like I am going to be playing games then. I am out of luck, and
    unfortunately I cannot change the clock to double the rate. Thanks
    for your reply.

    > Even without a PLL you can easily make a divider though to generate a
    > clock enable. If you can, change the oscillator to 2x of what you
    > have now and use that as your clock instead throughout the design.
    > Use the output of the divider as the clock enable for anything that
    > needs to run at the 1x speed.
    >
    > Kevin Jennings
    nfirtaps, Mar 14, 2007
    #3
  4. nfirtaps

    Homuncilus Guest

    On 3ÔÂ15ÈÕ, ÉÏÎç12ʱ22·Ö, "KJ" <> wrote:
    > On Mar 14, 11:59 am, "nfirtaps" <> wrote:> I am in the unfortunate situation of not having access to a PLL on my
    > > Altera and need to deserialize a DDR signal. It would be most
    > > advantageous to double the clock rate and sample on every rising edge
    > > to deserialze my DDR signal. I have read on this forum there are some
    > > circuits that do not require a PLL to double the clock (using some
    > > xors, nots and ff's), and I have implemented these circuits. They
    > > seem to be junk, and are very frequency dependant.

    >
    > Just curious, in what way are they 'junk'?
    >
    >
    >
    > > I have also read that you cannot take the clock, the inverted clock
    > > and deserialize using rising egde flip flops to sample the signal?
    > > Why is this?

    >
    > Usually it's because the duty cycle is not very well controlled by the
    > time it gets to the point where you need it so your 'falling' edge
    > doesn't occur anywhere near the midpoint of the clock cycle. Then
    > about all you can do is play games with resistors and capacitors to
    > try to tweak the edges to be just right....it's not a robust solution.
    >
    > Even without a PLL you can easily make a divider though to generate a
    > clock enable. If you can, change the oscillator to 2x of what you
    > have now and use that as your clock instead throughout the design.
    > Use the output of the divider as the clock enable for anything that
    > needs to run at the 1x speed.
    >
    > Kevin Jennings


    I have an idea about it which is delineated by verilog.
    Homuncilus, Mar 17, 2007
    #4
  5. nfirtaps

    KJ Guest

    > I have an idea about it which is delineated by verilog.

    Congratulations
    KJ, Mar 17, 2007
    #5
  6. nfirtaps

    Andy Guest

    On Mar 14, 10:59 am, "nfirtaps" <> wrote:
    > I have also read that you cannot take the clock, the inverted clock
    > and deserialize using rising egde flip flops to sample the signal?
    > Why is this?


    Depending on timing margins, and the particular FPGA architecture, you
    may be able to use inverted clock or not. On older xilinx
    architectures (V2 and older) there was a small skew between inverted
    clock input and "true" falling edge. Depending on your timing
    requirements, this may or may not work for you. IIRC, it was on the
    order of 40 ps. Newer xilinx parts distribute global clocks
    differentially, and there is no (signicifcant) skew, so they just
    work.

    Andy
    Andy, Mar 19, 2007
    #6
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