debugging a RTL design of an arithmetic coprocessor

[virgilpetcu]

Hello!

I'm doing a research project which consists in designing the pipeline & control of an interval arithmetic fp coprocessor.
I've written the RTL VHDL code for my part of the project and simple behavioral models for the functional units used & the reg file.Also I've successfully tested most of of the individual components designed.
Now i'm trying to test the whole coprocessor but there seem to be some bugs I can't find. I think the problem is the synchronization between the many processes I have, but i don't really have any experience in debugging a VHDL project of this magnitude so i could really use some tips.
Also i'd like to know if some features of ModelSim PE student edition could help me debug this design.

Thanks,
Virgil Petcu