# Decimal numbers

Discussion in 'VHDL' started by Tim Hubberstey, Apr 21, 2004.

1. ### Tim HubbersteyGuest

Ed wrote:
> When using std_logic_vectors(xx downto yy) I can use either binary numbers
> in the form "11010101" or hex numbers in the form x"00". How can I use
> decimal numbers?

Use type conversion functions:

library ieee;
use ieee.numeric_std.all;
....
signal some_vector : std_logic_vector(x-1 downto 0);
....
some_vector <= std_logic_vector(to_unsigned(DECIMAL_VAL, x);
or
some_vector <= std_logic_vector(to_signed(DECIMAL_VAL, x);

Limitations: Maximum value for 'x' is 31 for unsigned, 32 for signed.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Tim Hubberstey, Apr 21, 2004

2. ### EdGuest

Hello,

When using std_logic_vectors(xx downto yy) I can use either binary numbers
in the form "11010101" or hex numbers in the form x"00". How can I use
decimal numbers? I've done a google search but can't find any answers.

Thanks,

Ed, Apr 22, 2004

3. ### Thomas ReinemannGuest

Tim Hubberstey wrote:
> some_vector <= std_logic_vector(to_unsigned(DECIMAL_VAL, x);
> or
> some_vector <= std_logic_vector(to_signed(DECIMAL_VAL, x);

some_vector <= std_logic_vector(to_signed(DECIMAL_VAL,some_vector'length);

will automatically pass the right value to "to_signed". Of course you
can use it in "to_unsigned".

Regards,

Tom

Thomas Reinemann, Apr 22, 2004