Hi all
What is the most efficient way of writing an address decoder (VHDL)for a core?
The problem that i am facing now is the delay of the input address decoder.
The delay is pretty high that i am not able to meet the input constraints.
How should i model the input decoder? I have 15 address lines to address the different registers inside the core ? Also the core is having 8, 16 & 32 bit interface which again needs a multiplexer which adds to the input delay.
Thanks
dkk
What is the most efficient way of writing an address decoder (VHDL)for a core?
The problem that i am facing now is the delay of the input address decoder.
The delay is pretty high that i am not able to meet the input constraints.
How should i model the input decoder? I have 15 address lines to address the different registers inside the core ? Also the core is having 8, 16 & 32 bit interface which again needs a multiplexer which adds to the input delay.
Thanks
dkk