Decoder using VHDL

Discussion in 'VHDL' started by dkk1980, Apr 25, 2007.

  1. dkk1980

    dkk1980

    Joined:
    Apr 25, 2007
    Messages:
    1
    Hi all

    What is the most efficient way of writing an address decoder (VHDL)for a core?
    The problem that i am facing now is the delay of the input address decoder.
    The delay is pretty high that i am not able to meet the input constraints.

    How should i model the input decoder? I have 15 address lines to address the different registers inside the core ? Also the core is having 8, 16 & 32 bit interface which again needs a multiplexer which adds to the input delay.

    Thanks
    dkk
     
    dkk1980, Apr 25, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. jacobo
    Replies:
    4
    Views:
    1,212
    Marc Randolph
    May 19, 2004
  2. Wilq
    Replies:
    0
    Views:
    1,378
  3. Ved P Singh
    Replies:
    0
    Views:
    531
    Ved P Singh
    Apr 29, 2005
  4. afd
    Replies:
    1
    Views:
    8,365
    Colin Paul Gloster
    Mar 23, 2007
  5. mitsui9999

    VHDL HELP!!!!! Kepad decoder code

    mitsui9999, Oct 17, 2008, in forum: VHDL
    Replies:
    0
    Views:
    759
    mitsui9999
    Oct 17, 2008
Loading...

Share This Page