Delay Counter

Discussion in 'VHDL' started by nigel502@gmail.com, Jun 16, 2006.

  1. Guest

    Please forgive me - as I am very very new to VHDL - but I'm trying to
    get a LCD to work strictly in VHDL that uses a HLL (C/Java) to dump
    down a command - and then enters a delay loop. We decided that the loop
    was too costly and are trying to move it into vhdl. So I entered this
    loop into the section of the FSM where waiting needs to happen:

    x <= '1';
    for i in 5000 downto 0 loop
    x <= not x;
    end loop;

    However this loop isn't synthesised, in fact when we flash the chip it
    skips over it stating that the sof files are the same. I'm assuming
    that you can't syntesize a delay loop?

    My next question is how do I create and subsequently call a counter
    that will satisfy my requirments. Say I need a 500ns delay - how do I
    call this from the procedure that houses the FSM?
    , Jun 16, 2006
    #1
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  2. D Stanford Guest

    > My next question is how do I create and subsequently call a counter
    > that will satisfy my requirments. Say I need a 500ns delay - how do I
    > call this from the procedure that houses the FSM?


    What you need is a synchronous counter, and it's easy to do:

    process(clk, reset)
    if reset = '1' then
    counter <= (others => '0')
    elsif clk'event and clk = '1' then -- or rising_edge(clk)
    if counter_en = '1'
    counter <= counter + 1;
    end if;
    end if;
    end process;

    What you need to define is what is the clock rate? What input do I have
    that I can use to enable the counter? What output from the counter do I
    want to use? What do I want the counter do do when I'm not using it?
    D Stanford, Jun 16, 2006
    #2
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  3. hey buddy,
    u just have to do is. reset the counter with the required sequence. n
    then
    assign it within the clock. i mean to say u can make the ring counter
    which will provide u with the sequence generator.

    signal seq: std_logic_vector (3 downto 0);

    process( clk)

    begin

    if ( reset = '1')
    seq <= "0101";
    elsif (clk'event and clk = '1') then
    seq <= seq (0) & seq( 3 downto 1);
    end if ;

    end process;

    i hope its write. neways am writting code in VHDL aftr 2 years.
    if am wrong pls correct me.



    D Stanford wrote:
    > > My next question is how do I create and subsequently call a counter
    > > that will satisfy my requirments. Say I need a 500ns delay - how do I
    > > call this from the procedure that houses the FSM?

    >
    > What you need is a synchronous counter, and it's easy to do:
    >
    > process(clk, reset)
    > if reset = '1' then
    > counter <= (others => '0')
    > elsif clk'event and clk = '1' then -- or rising_edge(clk)
    > if counter_en = '1'
    > counter <= counter + 1;
    > end if;
    > end if;
    > end process;
    >
    > What you need to define is what is the clock rate? What input do I have
    > that I can use to enable the counter? What output from the counter do I
    > want to use? What do I want the counter do do when I'm not using it?
    dipesh.trivedi, Jun 19, 2006
    #3
  4. hi there,
    i think David is right, the thing you have to do is, u have to count
    the clock cycle to make the delay in ckt. for that u must know the clk
    frquency n then decide the min. no. of flip-flop u wil require to
    count. for eg. if ur clock period is 50ns then u have to count 100 for
    5000ns delay. aftr counting 100 set the flag which directs u to the nxt
    state.
    i hope it wil work n it is synthesisable.

    what do u say David?
    m i right? if not then pls correct me.
    wil be waiting for ur reply.



    D Stanford wrote:
    > > My next question is how do I create and subsequently call a counter
    > > that will satisfy my requirments. Say I need a 500ns delay - how do I
    > > call this from the procedure that houses the FSM?

    >
    > What you need is a synchronous counter, and it's easy to do:
    >
    > process(clk, reset)
    > if reset = '1' then
    > counter <= (others => '0')
    > elsif clk'event and clk = '1' then -- or rising_edge(clk)
    > if counter_en = '1'
    > counter <= counter + 1;
    > end if;
    > end if;
    > end process;
    >
    > What you need to define is what is the clock rate? What input do I have
    > that I can use to enable the counter? What output from the counter do I
    > want to use? What do I want the counter do do when I'm not using it?
    dipesh.trivedi, Jun 19, 2006
    #4
  5. On 18 Jun 2006 23:58:18 -0700, "dipesh.trivedi"
    <> wrote:

    >i hope it wil work n it is synthesisable.
    >
    >what do u say David?
    >m i right? if not then pls correct me.
    >wil be waiting for ur reply.


    Can someone kindly explain to me why it is appropriate to
    write "synthesisable" in full, and then use the ugly text-speak
    abbreviations "u", "ur", "m" and so on? Do our readers
    not deserve the courtesy of a decently written response?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jun 19, 2006
    #5

  6. > Can someone kindly explain to me why it is appropriate to
    > write "synthesisable" in full, and then use the ugly text-speak
    > abbreviations "u", "ur", "m" and so on? Do our readers
    > not deserve the courtesy of a decently written response?
    > --
    > Jonathan Bromley, Consultant


    dnt think so. this group is for sharing knowledge n not to show the
    spelling mistakes or grammer mistakes.
    i think u shud b a english language consultant rather then techno
    consultant.

    so pls if u r nt solving or helping to solve problems here in
    technology.
    then jus dnt reply MY DEAR FRIEND.
    dipesh.trivedi, Jun 19, 2006
    #6
  7. D Stanford Guest


    > dnt think so. this group is for sharing knowledge n not to show the
    > spelling mistakes or grammer mistakes.
    > i think u shud b a english language consultant rather then techno
    > consultant.


    And in sharing knowledge, ones speech and writing implies things about
    them as well. It can be much easier to take someone seriously when
    they're grammar and spelling attempt to be correct instead of using
    'text' or 'l33t' speek, since these are typically not used in a
    professional setting.
    D Stanford, Jun 19, 2006
    #7
  8. Rtafas Guest

    You shoud read about digital systems and take some look on synchrous
    digital logic. Another point is search about sequential/concurrent
    statements. You cannot understand this problem of yours without this
    background.

    After those reading, lets say that the compiler check this code this
    way, if it is not within a process: the same time x gets 1, it gets
    5001 times not x. and x can't have 5002 sources at the SAME time.

    Regards

    Rtafas


    wrote:
    > Please forgive me - as I am very very new to VHDL - but I'm trying to
    > get a LCD to work strictly in VHDL that uses a HLL (C/Java) to dump
    > down a command - and then enters a delay loop. We decided that the loop
    > was too costly and are trying to move it into vhdl. So I entered this
    > loop into the section of the FSM where waiting needs to happen:
    >
    > x <= '1';
    > for i in 5000 downto 0 loop
    > x <= not x;
    > end loop;
    >
    > However this loop isn't synthesised, in fact when we flash the chip it
    > skips over it stating that the sof files are the same. I'm assuming
    > that you can't syntesize a delay loop?
    >
    > My next question is how do I create and subsequently call a counter
    > that will satisfy my requirments. Say I need a 500ns delay - how do I
    > call this from the procedure that houses the FSM?
    Rtafas, Jun 19, 2006
    #8
  9. dipesh.trivedi wrote:

    > so pls if u r nt solving or helping to solve problems here in
    > technology.
    > then jus dnt reply



    Post whatever you like,
    but consider that you may be reducing
    the pool of potential question-answering readers
    to the very few who write with your particular style.

    -- Mike
    Mike Treseler, Jun 19, 2006
    #9
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