Delay counters in three process state machines

Discussion in 'VHDL' started by thecolororange, Jun 26, 2009.

  1. thecolororange

    thecolororange

    Joined:
    Jun 26, 2009
    Messages:
    2
    I'm trying to change some existing code to improve timing and the quality of the code in general. One of the ways I'm trying to do this is switching from using a single process for a state machine to dividing it into 3 processes (state advance, output, state change).

    I'm having trouble with one part of the code, though. In several states, there are delays generated by using a simple counter, like the following:

    Code:
    	when READ_2 =>
    		if wait_ctr = 2 then
    			wait_ctr <= 0;
    			sram_clk <= '1';
    			ram_action    <= READ_DATA;
    			access_state <= READ_3;
    		else
    			wait_ctr <= wait_ctr + 1;
    		end if;
    
    These worked fine when there was only one process, since that process was the only place I used or modified wait_ctr. With three processes, only the state advancement (access_state <= next_state;) process gets a clock, so it has to increment the counter, but only the state change process or output process would know when to reset wait_ctr, and both processes can't drive that signal.

    If wait_ctr was always reset at the same max value, I'd be fine, but it's used in several places with different max values. Is the answer that I need different signals for the counters? Is generating delays like this bad practice? Is there a better way? I appreciate any input.
    thecolororange, Jun 26, 2009
    #1
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  2. thecolororange

    cheevu

    Joined:
    Jan 9, 2008
    Messages:
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    Location:
    BAngalore
    u can use wait_ctr as a free running counter provided all the three process need wait_ctr to be start at same time period.
    cheevu, Jul 2, 2009
    #2
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