Delay of control signals

[Ingmar Seifert]

Hello,

As desribed some threads above I have a multplier an adder and a
registerbank in a row.
I furtermore have a FSM that generates controlsignals for the
operand-multiplexers of each unit.

To control one run through this row I have to set the mul-control-signal
at first, one clock later the add-control-signal and two clock cycles
later the control-signal that chooses the location to store the result
of the run.

At the moment I set in state1 the mul-control-signal in state2 the
add-control-signal and in state3 the capture-control-signal.

Is it a common way to set all control-signals in one state and delay
them (with D-FlipFlops) by one and two clock cycles?



Thanks in advance.
Ingmar Seifert