Delaying vectors with an array

Discussion in 'VHDL' started by Cesar, Jul 16, 2008.

  1. Cesar

    Cesar Guest

    Hello:

    I have tried to introduce clock-cycle delays in a vector with the
    following VHDL code, which uses an array of vectors. The result of
    simulating it with ModelSim is that the vector_delayed array contains
    'X's (undefined) instead of '1's (ones) all the time. On the other
    hand, '0's (zeros) are OK.

    constant DELAY: integer := 5;
    type vector_array_t is array (0 to DELAY) of std_logic_vector(10
    downto 0);
    signal vector_delayed: vector_array_t := (others => (others => '0'));
    signal vector_input: std_logic_vector(10 downto 0);
    alias vector_output: std_logic_vector(10 downto 0) is
    vector_delayed(DELAY);
    vector_delayed(0) <= vector_input;
    delay_proc: process(clk)
    begin
    if clk'event and clk = '1' then
    for i in 1 to DELAY loop
    vector_delayed(i) <= vector_delayed(i - 1);
    end loop;
    end if;
    end process;


    Using the following VHDL code for simulation with ModelSim, it works
    as OK. That is, with '1' and '0' in the vector_delayed array.

    constant DELAY: integer := 5;
    type vector_array_t is array (1 to DELAY) of std_logic_vector(10
    downto 0);
    signal vector_delayed: vector_array_t := (others => (others => '0'));
    signal vector_input: std_logic_vector(10 downto 0);
    alias vector_output: std_logic_vector(10 downto 0) is
    vector_delayed(DELAY);
    delay_proc: process(clk)
    begin
    if clk'event and clk = '1' then
    for i in 1 to DELAY loop
    if i = 1 then
    vector_delayed(i) <= vector_input;
    else
    vector_delayed(i) <= vector_delayed(i - 1);
    end if;
    end loop;
    end if;
    end process;


    Do anyone know why this happens?

    Regards,
    Cesar
     
    Cesar, Jul 16, 2008
    #1
    1. Advertising

  2. Cesar

    Tricky Guest

    'X's are the results of driving the same std_logic from two different
    sources. My guess is you are driving vector_delayed(0) from
    vector_input and somewhere else. The best way to catch this would be
    to declare everything as std_ulogic_vectors as they only allow 1
    source, and the compiler will throw an error if they are being driven
    from multiple locations.

    In the second instance you are missing vector_delayed(0) out
    completly, and so the shift register will be 1 register shorter than
    the top shift register.
     
    Tricky, Jul 16, 2008
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Rootz Anabo
    Replies:
    13
    Views:
    933
    Nicolas Matringe
    Apr 9, 2004
  2. dcreddy1980

    problem in delaying the input bit??

    dcreddy1980, Dec 15, 2004, in forum: VHDL
    Replies:
    6
    Views:
    443
    dcreddy1980
    Dec 15, 2004
  3. Marcin
    Replies:
    2
    Views:
    645
    Christopher Benson-Manica
    Apr 16, 2004
  4. Replies:
    3
    Views:
    725
    Shadowman
    Mar 26, 2008
  5. Guest
    Replies:
    0
    Views:
    481
    Guest
    Sep 14, 2005
Loading...

Share This Page