Delaying vectors with an array

[Cesar]

Hello:

I have tried to introduce clock-cycle delays in a vector with the
following VHDL code, which uses an array of vectors. The result of
simulating it with ModelSim is that the vector_delayed array contains
'X's (undefined) instead of '1's (ones) all the time. On the other
hand, '0's (zeros) are OK.

constant DELAY: integer := 5;
type vector_array_t is array (0 to DELAY) of std_logic_vector(10
downto 0);
signal vector_delayed: vector_array_t := (others => (others => '0'));
signal vector_input: std_logic_vector(10 downto 0);
alias vector_output: std_logic_vector(10 downto 0) is
vector_delayed(DELAY);
vector_delayed(0) <= vector_input;
delay_proc: process(clk)
begin
if clk'event and clk = '1' then
for i in 1 to DELAY loop
vector_delayed(i) <= vector_delayed(i - 1);
end loop;
end if;
end process;


Using the following VHDL code for simulation with ModelSim, it works
as OK. That is, with '1' and '0' in the vector_delayed array.

constant DELAY: integer := 5;
type vector_array_t is array (1 to DELAY) of std_logic_vector(10
downto 0);
signal vector_delayed: vector_array_t := (others => (others => '0'));
signal vector_input: std_logic_vector(10 downto 0);
alias vector_output: std_logic_vector(10 downto 0) is
vector_delayed(DELAY);
delay_proc: process(clk)
begin
if clk'event and clk = '1' then
for i in 1 to DELAY loop
if i = 1 then
vector_delayed(i) <= vector_input;
else
vector_delayed(i) <= vector_delayed(i - 1);
end if;
end loop;
end if;
end process;


Do anyone know why this happens?

Regards,
Cesar

 

[Tricky]

'X's are the results of driving the same std_logic from two different
sources. My guess is you are driving vector_delayed(0) from
vector_input and somewhere else. The best way to catch this would be
to declare everything as std_ulogic_vectors as they only allow 1
source, and the compiler will throw an error if they are being driven
from multiple locations.

In the second instance you are missing vector_delayed(0) out
completly, and so the shift register will be 1 register shorter than
the top shift register.