Deliberate output glitches

Discussion in 'VHDL' started by claire_ess, May 2, 2004.

  1. claire_ess

    claire_ess Guest

    I know that its highly frowned upon but I need to produce an output from an
    cpld which is very short in duration,in the order of 0.5 ns,the problem
    being that my main clock is very slow at 10 Khz.I have tried the idea of
    introducing a deliberate glitch by putting some number of nots in one
    input to an AND gate but unfortunatly even with the synthesis off pragma I
    cannot get XST to synthesise the logic without complaining.I know that my
    method is highly dependant on temperature and voltage but can anyone
    suggest how I can make XST synthesise without complaining?
    Thanks
     
    claire_ess, May 2, 2004
    #1
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  2. I can't speak for XST especially but using 'keep' as an attribute can
    help you further I guess.
    Have a look in the manual about attributes.

    Regards,

    Luc

    On Sun, 02 May 2004 15:53:31 -0400, "claire_ess"
    <> wrote:

    >I know that its highly frowned upon but I need to produce an output from an
    >cpld which is very short in duration,in the order of 0.5 ns,the problem
    >being that my main clock is very slow at 10 Khz.I have tried the idea of
    >introducing a deliberate glitch by putting some number of nots in one
    >input to an AND gate but unfortunatly even with the synthesis off pragma I
    >cannot get XST to synthesise the logic without complaining.I know that my
    >method is highly dependant on temperature and voltage but can anyone
    >suggest how I can make XST synthesise without complaining?
    >Thanks
     
    Luc Braeckman, May 7, 2004
    #2
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