Delta Count Overflow in Simulation

Discussion in 'VHDL' started by Isaac, Aug 14, 2003.

  1. Isaac

    Isaac Guest

    Hi Guys,
    I have to block I have to interconnect the two in such a way that the
    input of one block is the output from other one . You can think of as
    a loop.
    I have separate entities for these two block and in the top entity I
    have declared the two components and I used port mapping to connect
    the signals. For this say I have defined signals and I am using this
    signal as to port map the input of first block and at the same time I
    am using the same signal to port map the output of second block.
    when I start doing simulation I got the following error.
    ----------------------------
    Delta count overflow - stopped. Try to increase the iterations limit
    in simulator preferences.
    # Fatal error occurred during simulation
    --------------------------------

    Now I think that since I have just used one signal to port map the
    input and output of first and second block respectively, that might be
    causing the infinite loop. Do you think I need to defined signal for
    both entities separetly and then use the state machine to pass the
    signal from one block to another.
    Is this is the way to do it or you have some other suggestions?

    Any help would be appreciated.

    Cheers


    Isaac
     
    Isaac, Aug 14, 2003
    #1
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  2. Isaac

    Jon Guest

    Hi Isaac,
    "Usually" when you get that error there is some type of feedback
    loop. It does not have anything to do using the same single in the
    port map for the driver and the receiver. Check to make sure that you
    do not have a combinational feedback path.

    Jon

    (Isaac) wrote in message news:<>...
    > Hi Guys,
    > I have to block I have to interconnect the two in such a way that the
    > input of one block is the output from other one . You can think of as
    > a loop.
    > I have separate entities for these two block and in the top entity I
    > have declared the two components and I used port mapping to connect
    > the signals. For this say I have defined signals and I am using this
    > signal as to port map the input of first block and at the same time I
    > am using the same signal to port map the output of second block.
    > when I start doing simulation I got the following error.
    > ----------------------------
    > Delta count overflow - stopped. Try to increase the iterations limit
    > in simulator preferences.
    > # Fatal error occurred during simulation
    > --------------------------------
    >
    > Now I think that since I have just used one signal to port map the
    > input and output of first and second block respectively, that might be
    > causing the infinite loop. Do you think I need to defined signal for
    > both entities separetly and then use the state machine to pass the
    > signal from one block to another.
    > Is this is the way to do it or you have some other suggestions?
    >
    > Any help would be appreciated.
    >
    > Cheers
    >
    >
    > Isaac
     
    Jon, Aug 14, 2003
    #2
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  3. Isaac

    Arvind Kumar Guest

    Hi,
    You did not mention which simulator you're using! What you
    mentioned in your mail, cannot cause delta count overflow. My guess is
    you have combinational loop in your design somewhere. You could try
    locating this in the design. If you're using Modelsim, use set
    IterationLimit command to increase the delta count. By default, I
    think modelsim uses 5000 iterations..You could set it to 10000 and run
    it once again..!!!
    Hope this helps..
    Regards,
    Arvind Kumar,
    Sr. Design Engineer,
    Sasken Communication Technologies Ltd.
    Bangalore, INDIA


    (Jon) wrote in message news:<>...
    > Hi Isaac,
    > "Usually" when you get that error there is some type of feedback
    > loop. It does not have anything to do using the same single in the
    > port map for the driver and the receiver. Check to make sure that you
    > do not have a combinational feedback path.
    >
    > Jon
    >
    > (Isaac) wrote in message news:<>...
    > > Hi Guys,
    > > I have to block I have to interconnect the two in such a way that the
    > > input of one block is the output from other one . You can think of as
    > > a loop.
    > > I have separate entities for these two block and in the top entity I
    > > have declared the two components and I used port mapping to connect
    > > the signals. For this say I have defined signals and I am using this
    > > signal as to port map the input of first block and at the same time I
    > > am using the same signal to port map the output of second block.
    > > when I start doing simulation I got the following error.
    > > ----------------------------
    > > Delta count overflow - stopped. Try to increase the iterations limit
    > > in simulator preferences.
    > > # Fatal error occurred during simulation
    > > --------------------------------
    > >
    > > Now I think that since I have just used one signal to port map the
    > > input and output of first and second block respectively, that might be
    > > causing the infinite loop. Do you think I need to defined signal for
    > > both entities separetly and then use the state machine to pass the
    > > signal from one block to another.
    > > Is this is the way to do it or you have some other suggestions?
    > >
    > > Any help would be appreciated.
    > >
    > > Cheers
    > >
    > >
    > > Isaac
     
    Arvind Kumar, Aug 18, 2003
    #3
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