delta cycle?? (delta delay)

Discussion in 'VHDL' started by srikanth.padava, Feb 28, 2008.

  1. srikanth.padava

    srikanth.padava

    Joined:
    Feb 28, 2008
    Messages:
    3
    I have a basic question regarding the delta cycle. It has really got on to my head now. I hope some one could help me out with this.

    It was described in a post that a
    1. delta cycle = evaluation phase+update phase.
    2. and i have read that a signal gets updated only after one delta cycle delay.
    i.e if a process has a stmt a=1;(im using systemc) and deltacount =0, it should be updated in the next cycle.
    3. but from a post, if stmt a=1 gets evaluated in the present deltacycle, and gets updated in the update phase(which is also in the same deltacycle, as it was told that delta cycle = evaluation phase+update phase.)

    it would be great if some one explains me where ive got it wrong.

    thanx a lot in advance,

    srikanth.
     
    srikanth.padava, Feb 28, 2008
    #1
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