Denali Verification Webcast Series with Sean Smith Dec 15-16

Discussion in 'VHDL' started by Sean W, Smith, Dec 7, 2004.

  1. Usenet Verilog and VHDL Users,

    As some of you may already know I have moved on from my
    role at Cisco systems to be the Chief Verification Architect at Denali
    Software Inc. The rest of this message is some shameless self
    promotion that may be of interest to the verification engineers on this
    list. :) Denali is hosting a two part webcast series where I will
    discuss todays verification challenges and where verification is going.
    This is NOT A PRODUCT PITCH for any Denali product but instead some
    commentary on the challenges of verification and techniques to deal
    with them. Most of the techniques and methodologies I will talk about
    were implemented in Specman during my previous job but are applicable
    to any implementation vehicle engineers decide to use. I hope that
    some of you may choose to attend and provide some feedback on what you
    hear... More details below... Each of these webcast will be ~40

    Sean Smith
    Chief Verification Architect
    Denali Software Inc.

    Denali Verification Webcast Series:

    Part 1: December 15, 2004, 11:00 AM PST
    Verification Infrastructures for IP-Based Methodologies

    Abstract: Intellectual property (IP) is one of the primary keys to
    enabling massive SoC designs. The use of commercial IP seems simple and
    easy at the surface, but there are a number of critical methodology
    issues that must addressed before the value of IP can be realized.
    Physical issues aside, a cursory look at the functional aspect of
    verifying and integrating IP reveals some opportunities for significant
    strides towards a meaningful methodology using state-of-the art
    verification technologies. This webcast will address configurable
    verification IP requirements, coverage techniques, test generation,
    compliance, and strategies and tactics for implementing a verification
    reuse methodology.

    Part 2: December 16, 2004, 11:00 AM PST
    Verification Reuse and Beyond: System Level Verification

    Abstract: This webcast goes beyond the advanced verification reuse
    techniques presented in Part 1, and looks at where leading edge
    verification is going. We will explore new technologies designed to
    further push the limits of what is possible in terms of verification
    productivity and quality. These techniques extend beyond what
    traditional verification techniques encompass and attack certain
    aspects of design quality and productivity to deliver the next big step
    in verification productivity. This presentation will cover configurable
    IP generators, formal descriptions of design and verification IP, as
    well as industry initiatives such as SPIRIT. Don't miss this
    opportunity to get a glimpse of where design and verification
    techniques are headed.
    Sean W, Smith, Dec 7, 2004
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