Design Built-in Self Test

Discussion in 'VHDL' started by abhishekshishodia, Jul 23, 2011.

  1. Hello freinds,

    I am final yr. graduating student of enginnering. I have to do a major
    project for which I have decided to design Built-in self test fo
    memory testing.
    Please tell me how could I design memory(eg. RAM) in VHDL. I only know
    that I could need ModelSIM and synopsys software dc_shell for doing
    this. Please tell me how could I implement RAM in VHDL and then design
    a built-in self test for testing that memory.

    -Abhishek
     
    abhishekshishodia, Jul 23, 2011
    #1
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  2. abhishekshishodia

    KJ Guest

    On Jul 23, 2:05 am, abhishekshishodia
    <> wrote:
    > Hello freinds,
    >
    > I am final yr. graduating student of enginnering. I have to do a major
    > project for which I have decided  to design Built-in self test fo
    > memory testing.
    > Please tell me how could I design memory(eg. RAM) in VHDL. I only know
    > that I could need ModelSIM and synopsys software dc_shell for doing
    > this. Please tell me how could I implement RAM in VHDL and then design
    > a built-in self test for testing that memory.
    >


    Try using Google
    http://lmgtfy.com/?q=how could I implement RAM in VHDL and then design

    Some examples that pop out
    http://quartushelp.altera.com/current/mergedProjects/hdl/vhdl/vhdl_pro_ram_inferred.htm
    http://vhdlguru.blogspot.com/2011/01/block-and-distributed-rams-on-xilinx.html

    KJ
     
    KJ, Jul 23, 2011
    #2
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