S
synop_user
I've tried using Design Compiler's "Automated Chip Synthesis"
feature. I have been able to complete the tutorial, and
transfer the "ACS flow" onto a current in-house project.
Now I'm completely lost. Why would I want to use ACS over
a conventional top/down or bottom/up compile? So far,
the only practical advantage of ACS is that I don't have
to manually do "read -f verilog file1.v; ... file5.v."
ACS will scan a directory of *.v files, and all I have to
do is type "acs_read_hdl <name_of_top_module>."
My site is not licensed for Physical Compiler or any of
Synopsys's physical/back-end stuff.
feature. I have been able to complete the tutorial, and
transfer the "ACS flow" onto a current in-house project.
Now I'm completely lost. Why would I want to use ACS over
a conventional top/down or bottom/up compile? So far,
the only practical advantage of ACS is that I don't have
to manually do "read -f verilog file1.v; ... file5.v."
ACS will scan a directory of *.v files, and all I have to
do is type "acs_read_hdl <name_of_top_module>."
My site is not licensed for Physical Compiler or any of
Synopsys's physical/back-end stuff.