design error

Discussion in 'VHDL' started by HaYZaM, Dec 28, 2007.

  1. HaYZaM

    HaYZaM

    Joined:
    Nov 5, 2007
    Messages:
    5
    i am designing a 5 bit counter
    when the input INC = 1 , it increments 1 to the value in the counter away from the clock

    Code:
    ENTITY Project_SQ_generator IS
      port ( inc, arst : in std_logic;
             cnt       : out std_logic_vector(4 downto 0) );
    END ENTITY Project_SQ_generator;
    
    --
    ARCHITECTURE RTL OF Project_SQ_generator IS
    
    signal cnt_temp : unsigned(4 downto 0);
    
    BEGIN
    
      process (inc,arst)
      begin
          if arst = '1' then cnt_temp <="00000";
          elsif inc = '1' then
            cnt_temp <= cnt_temp +1;
          end if;
      end process;
    
    cnt <= std_logic_vector(cnt_temp);
            
    END ARCHITECTURE RTL;
    
    
    HaYZaM, Dec 28, 2007
    #1
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