design flow xilinx ise 7.1+synplify pro8.4

[prakash.na]

Hi,
While porting hdl codes in xilinx, I synthesized using synplify with my
constraints.Then I place& routed in xilinx-ISE the edif file (output
of synplify). Now there are some timing errors coming in ise. Now I
want to view the P&R 'ed file in synplify, which file I 've to load it
in synplify. Is it possible to use synplify as the synthesis tool in
ise (wher to set).
One more doubt is in synplify I could see its mapping also. Again when
I try to P&R the xilinx also maps. In the error in ISE it says try map
-timing option. Is it required even if we do auto constrain freq in
synthesis using synplify.
Please clarify
Prakash

 

[Mike Treseler]

While porting hdl codes in xilinx, I synthesized using synplify with my
constraints.Then I place& routed in xilinx-ISE the edif file (output
of synplify). Now there are some timing errors coming in ise.

Synthesis timing before place & route cannot be very accurate.
I prefer to constrain and view the back end.

Now I
want to view the P&R 'ed file in synplify, which file I 've to load it
in synplify. Is it possible to use synplify as the synthesis tool in
ise (wher to set).

Once Synplify has generated an .edf file, it is done.
Consider using the ISE STA and viewers to do the rest.

-- Mike Treseler

 

[Arnaud]

Hello,

I would like to come back on one of Prakash questions : "Is it possible
to use synplify as the synthesis tool in
ise". I'm having quite the same problem and I would be very interested
in the answers.

Actually, I'm using a V2p70 on which I'm using the PPC + OPB/PLB buses
+ IPIF interface, etc.. I've also written my own VHDL IPs which are
connected to the OPB bus.

For the moment, I'm synthesizing these IPs using Synplify, and then I
use the edif netlist in ISE to connect with the other IPs and launch
P&R.

However, I would like to know if it is possible to use Synplify as the
default synthesise tool in ISE instead of the not-so-good XST tool.
That would permit to achieve better performance as Synplify could
synthesize the whole system-on-chip instead of the VHDL part only (the
last versions of Synplify are able to read back edf, edn or ngc
netlists and make optimizations in those).

Has anyone experienced the same problem ? Could you give me, or more
exactly give us, some information on how to do it?

Thanks a lot.

Regards,

Arnaud