Design of Usart(synchronous) in Vhdl using Quartus

Discussion in 'VHDL' started by athulyapg, Aug 18, 2006.

  1. athulyapg

    athulyapg

    Joined:
    Aug 18, 2006
    Messages:
    2
    Hi ,

    Can anyone tell me what are the steps in design of synchronous serial communication and testing using Quartus. The target device is CPLD (Altera)
    athulyapg, Aug 18, 2006
    #1
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