Hi Andy,
When in Rome, do as the Romans do. If your team is expecting a top level schematic, you'll probably have to give it to them, at least until you can demonstrate alternate means of giving them the "benefits" they currently think they get from a top level schematic.
I can see a clear "benefit" if you have to explain your design to
somebody not familiar with your design.
I started out using schematics a long time ago. After initially resisting VHDL, I embraced it and would NEVER go back!
The point is that you are not going back, tool and technology evolve and
so have graphical design entry tools (although they are actually design
entry and management tools to use the proper marketing term, graphics is
only a small part of their capabilities). We are not talking about
connecting AND/OR gate together, we are talking about parts of the
design process which can benefit from schematics.
I will not allow developers to use a schematic at any level to generate their RTL.
Glad I am not working for you ;-)
Schematics generate the VHDL code that may "look pretty", but machine-generated VHDL is not maintainable (unless it can modify the schematic per RTL code changes),
With modern design entry tools the sole aim is to generate perfect RTL,
the output of the tool is VHDL/Verilog not schematics! The schematic is
just a method to help you create your RTL.
so you have to maintain the schematic,
No why? I often use my design entry tool to connect some blocks
together, generate a testbench framework, or an FSM and then I continue
in VHDL, this is quicker and less error prone then doing it manually.
which then raises some other questions that should be evaluated:
Is the schematic tool freely distributable (not just the viewer)?
AFAIK no, most viewers are.
Does the schematic provide for generate statements?
Yes.
Does the schematic provide for top-level generics?
Of course.
What about code comments?
Real man don't use comments....
Clearly you have never looked at a modern (graphical) design entry tool.
There are also techniques that can be used to simplify a purely structural VHDL architecture to provide some of the understandability of a WELL-CRAFTED schematic. Use more complex data types than SL & SLV to group related signals together (doues your schematic tool do that?)
Yes, you can use records.
By the time the user generates symbols for each underlying component/entity, and places them and connects them, naming each net, in a WELL CRAFTED schematic, they will have spent FAR more time than writing the code.
Again, you should really have a look at a modern design entry tool. The
symbols are generated automatically, connecting them can be done with a
single mouse click. The funny thing is that I now find it very tedious
to connect blocks manually, it is much quicker to let the tool do it for
me. The same applies to FSM, if somebody doesn't like my n-process FSM,
no problem a few mouse clicks and I have an m-process one.
I have yet to see a decent "beautifier" for schematics.
yes, don't believe there are any, I have also never seen a tool that can
create nice graphics from RTL no matter how expensive they are.
mmmmm, I wouldn't say plenty and the once I looked at all have issues.
However, it takes a lot more than a beautifier to create human-understandable VHDL. Good coding standards, coding for function rather than netlist, etc. go a long way.
I agree and for this reasons most design entry tools will give you a lot
of options to generate the code you want, again these tools are designed
to generate RTL not schematics. Some of the design entry tool also
provide linting capabilities so you can check that your code is adhering
to your coding standards.
As previously noted, there are good tools for generating graphical documentation from RTL: Sigasi (my favorite), DVT-Eclipse, Understand (sci-tools) and many synthesis tools.
If you like these tools then you will be amazed what a high-end
purposely designed design entry tool can do for you. Unfortunately as I
mentioned in my previous post you need a healthy EDA budget to purchase
them.
Displaying single-stepped simulation results on a schematic has got to be the worst excuse I have ever heard! That sounds like something a marketing manager would want to see (or a tool vendor would talk up).
So when you use your simulator (assuming Modelsim) do you use the list
window or do you look at the waveform window, perhaps the FSM window or
dataflow window? If you look at simulator development over the years you
will see more and more graphical windows. Mentor's Questa includes a
schematic window similar to what you get from a synthesis tool.
The point is that graphics may help you debug your code being it by back
annotating your simulation results on a block diagram or even animation
of your FSM (exists). I am not advocating people should use them, I
would just say use whatever works for you.
I can understand why somebody might be sceptical but to re-iterate my
point, these are tools to help you design your RTL, they are not moving
your design into some graphical tools domain from which there is no
escape. The output is always nicely formatted, readable, editable RTL as
that is what they are designed for.
Now back to debugging my SystemC code with printf statements....
Regards,
Hans.
www.ht-lab.com